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Added i:, o:, and x: selection pattern

This commit is contained in:
Clifford Wolf 2014-02-06 19:35:33 +01:00
parent d7d1c7baf8
commit 9428050dd6
1 changed files with 18 additions and 0 deletions
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18
passes/cmds/select.cc
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@ -657,6 +657,21 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
if (match_ids(it.first, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
} else
if (arg_memb.substr(0, 2) == "i:") {
for (auto &it : mod->wires)
if (it.second->port_input && match_ids(it.first, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
} else
if (arg_memb.substr(0, 2) == "o:") {
for (auto &it : mod->wires)
if (it.second->port_output && match_ids(it.first, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
} else
if (arg_memb.substr(0, 2) == "x:") {
for (auto &it : mod->wires)
if ((it.second->port_input || it.second->port_output) && match_ids(it.first, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
} else
if (arg_memb.substr(0, 2) == "m:") {
for (auto &it : mod->memories)
if (match_ids(it.first, arg_memb.substr(2)))
@ -836,6 +851,9 @@ struct SelectPass : public Pass {
log(" w:<pattern>\n");
log(" all wires with a name matching the given wildcard pattern\n");
log("\n");
log(" i:<pattern>, o:<pattern>, x:<pattern>\n");
log(" select input (i:), output (o:) or any ports (x:) with matching names\n");
log("\n");
log(" m:<pattern>\n");
log(" all memories with a name matching the given pattern\n");
log("\n");