mirror of https://github.com/YosysHQ/yosys.git
Added support for %m selection op
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@ -187,6 +187,14 @@ static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs)
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}
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}
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static void select_op_fullmod(RTLIL::Design *design, RTLIL::Selection &lhs)
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{
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lhs.optimize(design);
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for (auto &it : lhs.selected_members)
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lhs.selected_modules.insert(it.first);
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lhs.selected_members.clear();
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}
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static void select_op_union(RTLIL::Design*, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
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{
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if (rhs.full_selection) {
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@ -568,6 +576,11 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
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log_cmd_error("Must have at least one element on the stack for operator %%s.\n");
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select_op_submod(design, work_stack[work_stack.size()-1]);
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} else
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if (arg == "%m") {
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if (work_stack.size() < 1)
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log_cmd_error("Must have at least one element on the stack for operator %%s.\n");
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select_op_fullmod(design, work_stack[work_stack.size()-1]);
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} else
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if (arg == "%x" || (arg.size() > 2 && arg.substr(0, 2) == "%x" && (arg[2] == ':' || arg[2] == '*' || arg[2] == '.' || ('0' <= arg[2] && arg[2] <= '9')))) {
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if (work_stack.size() < 1)
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log_cmd_error("Must have at least one element on the stack for operator %%x.\n");
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@ -893,6 +906,9 @@ struct SelectPass : public Pass {
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log(" expand top set by adding all modules of instantiated cells in selected\n");
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log(" modules\n");
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log("\n");
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log(" %%m\n");
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log(" expand top set by selecting all modules that contain selected objects\n");
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log("\n");
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log("Example: the following command selects all wires that are connected to a\n");
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log("'GATE' input of a 'SWITCH' cell:\n");
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log("\n");
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