mirror of https://github.com/YosysHQ/yosys.git
flowmap: cleanup for clarity. NFCI.
This commit is contained in:
whitequark
parent
fd21564deb
commit
9bc5cf0844
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@ -402,29 +402,34 @@ struct FlowGraph
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struct FlowmapWorker
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{
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int order;
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pool<IdString> cell_types;
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bool debug;
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RTLIL::Module *module;
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SigMap sigmap;
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ModIndex index;
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pool<RTLIL::Cell*> cells;
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dict<RTLIL::SigBit, ModIndex::PortInfo> node_origins;
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pool<RTLIL::SigBit> nodes, inputs, outputs;
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dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges_fw, edges_bw;
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dict<RTLIL::SigBit, int> labels;
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dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_gates, lut_inputs;
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pool<RTLIL::SigBit> lut_nodes;
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dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_gates;
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dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_edges_fw, lut_edges_bw;
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dict<RTLIL::SigBit, ModIndex::PortInfo> node_origins;
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dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_fanout;
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int gate_count = 0, lut_count = 0, packed_count = 0;
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int gate_area = 0, lut_area = 0;
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int mapped_count = 0, packed_count = 0, unique_packed_count = 0;
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enum class GraphMode {
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Label,
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Cut,
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};
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void dump_dot_graph(string filename,
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void dump_dot_graph(string filename, GraphMode mode,
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pool<RTLIL::SigBit> subgraph_nodes = {}, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> subgraph_edges = {},
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pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> cut = {},
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dict<RTLIL::SigBit, pool<RTLIL::SigBit>> collapsed = {})
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dict<RTLIL::SigBit, pool<RTLIL::SigBit>> collapsed = {},
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pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> cut = {})
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{
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if (subgraph_nodes.empty())
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subgraph_nodes = nodes;
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@ -436,26 +441,29 @@ struct FlowmapWorker
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for (auto collapsed_node : collapsed[node])
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if (collapsed_node != node)
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label += stringf(" %s", log_signal(collapsed_node));
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if (labels[node] == -1)
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label += "\nl=?";
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else
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label += stringf("\nl=%d", labels[node]);
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if (cut.first.empty() && cut.second.empty())
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switch (mode)
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{
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if (labels[node] == -1)
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case GraphMode::Label:
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if (labels[node] == -1)
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{
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label += "\nl=?";
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return GraphStyle{label};
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}
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else
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{
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label += stringf("\nl=%d", labels[node]);
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string fillcolor = stringf("/set311/%d", 1 + labels[node] % 11);
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return GraphStyle{label, "", fillcolor};
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}
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case GraphMode::Cut:
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if (cut.first[node])
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return GraphStyle{label, "blue"};
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if (cut.second[node])
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return GraphStyle{label, "red"};
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return GraphStyle{label};
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string fillcolor = stringf("/set311/%d", 1 + labels[node] % 11);
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return GraphStyle{label, "", fillcolor};
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}
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else
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{
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string color = "black";
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if (cut.first[node])
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color = "blue";
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if (cut.second[node])
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color = "red";
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return GraphStyle{label, color};
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}
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return GraphStyle{label};
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};
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auto edge_style = [&](RTLIL::SigBit, RTLIL::SigBit) {
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return GraphStyle{};
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@ -519,57 +527,56 @@ struct FlowmapWorker
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return flow_graph;
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}
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FlowmapWorker(int order, pool<IdString> cell_types, bool debug, RTLIL::Module *module) :
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order(order), cell_types(cell_types), debug(debug), module(module), sigmap(module), index(module)
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void discover_nodes(pool<IdString> cell_types)
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{
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log("Labeling cells.\n");
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for (auto cell : module->selected_cells())
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{
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if (cell_types[cell->type])
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if (!cell_types[cell->type])
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continue;
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if (!cell->known())
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log_error("Cell %s (%s.%s) is unknown.\n", cell->type.c_str(), log_id(module), log_id(cell));
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pool<RTLIL::SigBit> fanout;
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for (auto conn : cell->connections())
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{
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if (!cell->known())
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if (!cell->output(conn.first)) continue;
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int offset = -1;
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for (auto bit : conn.second)
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{
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log_error("Cell %s (%s.%s) is unknown.\n", cell->type.c_str(), log_id(module), log_id(cell));
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offset++;
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if (!bit.wire) continue;
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auto mapped_bit = sigmap(bit);
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if (nodes[mapped_bit])
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log_error("Multiple drivers found for wire %s.\n", log_signal(mapped_bit));
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nodes.insert(mapped_bit);
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node_origins[mapped_bit] = ModIndex::PortInfo(cell, conn.first, offset);
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fanout.insert(mapped_bit);
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}
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cells.insert(cell);
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for (auto conn : cell->connections())
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{
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if (!cell->output(conn.first)) continue;
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int offset = -1;
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for (auto bit : conn.second)
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{
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offset++;
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if (!bit.wire) continue;
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auto mapped_bit = sigmap(bit);
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if (nodes[mapped_bit])
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log_error("Multiple drivers found for wire %s.\n", log_signal(mapped_bit));
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nodes.insert(mapped_bit);
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node_origins[mapped_bit] = ModIndex::PortInfo(cell, conn.first, offset);
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cell_fanout[cell].insert(mapped_bit);
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}
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}
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int fanin = 0;
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for (auto conn : cell->connections())
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{
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if (!cell->input(conn.first)) continue;
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for (auto bit : sigmap(conn.second))
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{
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if (!bit.wire) continue;
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for (auto fanout_bit : cell_fanout[cell])
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{
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edges_fw[bit].insert(fanout_bit);
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edges_bw[fanout_bit].insert(bit);
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}
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fanin++;
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}
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}
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if (fanin > order)
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log_error("Cell %s (%s.%s) with fan-in %d cannot be mapped to a %d-LUT.\n",
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cell->type.c_str(), log_id(module), log_id(cell), fanin, order);
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}
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int fanin = 0;
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for (auto conn : cell->connections())
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{
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if (!cell->input(conn.first)) continue;
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for (auto bit : sigmap(conn.second))
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{
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if (!bit.wire) continue;
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for (auto fanout_bit : fanout)
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{
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edges_fw[bit].insert(fanout_bit);
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edges_bw[fanout_bit].insert(bit);
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}
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fanin++;
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}
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}
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if (fanin > order)
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log_error("Cell %s (%s.%s) with fan-in %d cannot be mapped to a %d-LUT.\n",
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cell->type.c_str(), log_id(module), log_id(cell), fanin, order);
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gate_count++;
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gate_area += 1 << fanin;
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}
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for (auto edge : edges_fw)
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@ -591,15 +598,23 @@ struct FlowmapWorker
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outputs.insert(node);
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}
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if (debug)
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{
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dump_dot_graph("flowmap-initial.dot", GraphMode::Label);
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log("Dumped initial graph to `flowmap-initial.dot`.\n");
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}
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}
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void label_nodes()
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{
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for (auto node : nodes)
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labels[node] = -1;
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for (auto input : inputs)
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labels[input] = 0;
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if (debug)
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{
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dump_dot_graph("flowmap-initial.dot");
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log("Dumped complete initial graph to `flowmap-initial.dot`.\n");
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if (input.wire->attributes.count("\\$flowmap_level"))
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labels[input] = input.wire->attributes["\\$flowmap_level"].as_int();
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else
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labels[input] = 0;
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}
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pool<RTLIL::SigBit> worklist = nodes;
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@ -661,70 +676,73 @@ struct FlowmapWorker
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k.insert(xi_node_pred);
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}
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log_assert((int)k.size() <= order);
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lut_inputs[sink] = k;
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lut_edges_bw[sink] = k;
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for (auto k_node : k)
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lut_edges_fw[k_node].insert(sink);
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if (debug)
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{
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log(" Maximum flow: %d. Assigned label %d.\n", flow, labels[sink]);
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dump_dot_graph(stringf("flowmap-%d-sub.dot", debug_num), subgraph, {}, {x, xi});
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dump_dot_graph(stringf("flowmap-%d-sub.dot", debug_num), GraphMode::Cut, subgraph, {}, {}, {x, xi});
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log(" Dumped subgraph to `flowmap-%d-sub.dot`.\n", debug_num);
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flow_graph.dump_dot_graph(stringf("flowmap-%d-flow.dot", debug_num));
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log(" Dumped flow graph to `flowmap-%d-flow.dot`.\n", debug_num);
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log(" LUT packed:");
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for (auto xi_node : xi)
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log(" %s", log_signal(xi_node));
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log(".\n");
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log(" LUT inputs:");
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for (auto k_node : k)
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log(" %s", log_signal(k_node));
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log(".\n");
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log(" LUT packed gates:");
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for (auto xi_node : xi)
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log(" %s", log_signal(xi_node));
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log(".\n");
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}
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for (auto sink_succ : edges_fw[sink])
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worklist.insert(sink_succ);
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}
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int depth = 0;
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for (auto label : labels)
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depth = max(depth, label.second);
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log("Maximum depth: %d levels.\n", depth);
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if (debug)
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{
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dump_dot_graph("flowmap-labeled.dot");
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log("Dumped complete labeled graph to `flowmap-labeled.dot`.\n");
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dump_dot_graph("flowmap-labeled.dot", GraphMode::Label);
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log("Dumped labeled graph to `flowmap-labeled.dot`.\n");
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}
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}
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pool<RTLIL::SigBit> lut_nodes;
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dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_edges;
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worklist = outputs;
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int pack_luts()
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{
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pool<RTLIL::SigBit> worklist = outputs;
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while (!worklist.empty())
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{
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auto lut_node = worklist.pop();
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lut_nodes.insert(lut_node);
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for (auto input_node : lut_inputs[lut_node])
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{
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lut_edges[input_node].insert(lut_node);
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for (auto input_node : lut_edges_bw[lut_node])
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if (!lut_nodes[input_node] && !inputs[input_node])
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worklist.insert(input_node);
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}
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}
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int depth = 0;
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for (auto label : labels)
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depth = max(depth, label.second);
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log("Solved to %d LUTs in %d levels.\n", (int)lut_nodes.size(), depth);
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if (debug)
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{
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pool<RTLIL::SigBit> lut_and_input_nodes = lut_nodes;
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pool<RTLIL::SigBit> lut_and_input_nodes;
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lut_and_input_nodes.insert(lut_nodes.begin(), lut_nodes.end());
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lut_and_input_nodes.insert(inputs.begin(), inputs.end());
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dump_dot_graph("flowmap-packed.dot", lut_and_input_nodes, lut_edges, {}, lut_gates);
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log("Dumped complete packed graph to `flowmap-packed.dot`.\n");
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dump_dot_graph("flowmap-packed.dot", GraphMode::Label, lut_and_input_nodes, lut_edges_fw, lut_gates);
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log("Dumped packed graph to `flowmap-packed.dot`.\n");
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}
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return depth;
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}
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void map_cells()
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{
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ConstEval ce(module);
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for (auto input_node : inputs)
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ce.stop(input_node);
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log("\n");
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log("Mapping cells.\n");
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pool<RTLIL::SigBit> mapped_nodes;
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for (auto node : lut_nodes)
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{
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@ -759,7 +777,7 @@ struct FlowmapWorker
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log_id(module), log_id(gate_origin.cell), gate_origin.port.c_str(), gate_origin.offset, log_signal(gate_node));
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}
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vector<RTLIL::SigBit> input_nodes(lut_inputs[node].begin(), lut_inputs[node].end());
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vector<RTLIL::SigBit> input_nodes(lut_edges_bw[node].begin(), lut_edges_bw[node].end());
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RTLIL::Const lut_table(State::Sx, 1 << input_nodes.size());
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for (unsigned i = 0; i < (1 << input_nodes.size()); i++)
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{
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@ -786,7 +804,6 @@ struct FlowmapWorker
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lut_a.append_bit(input_node);
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RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table);
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mapped_count++;
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mapped_nodes.insert(node);
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for (auto gate_node : lut_gates[node])
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{
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@ -794,11 +811,11 @@ struct FlowmapWorker
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lut->add_strpool_attribute("\\src", gate_origin.cell->get_strpool_attribute("\\src"));
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packed_count++;
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}
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lut_count++;
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lut_area += 1 << input_nodes.size();
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log(" Packed into a %d-LUT %s.%s.\n", (int)input_nodes.size(), log_id(module), log_id(lut));
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}
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unique_packed_count += nodes.size();
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for (auto node : mapped_nodes)
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{
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auto origin = node_origins[node];
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@ -807,6 +824,19 @@ struct FlowmapWorker
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origin.cell->setPort(origin.port, driver);
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}
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}
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FlowmapWorker(int order, pool<IdString> cell_types, bool debug, RTLIL::Module *module) :
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order(order), debug(debug), module(module), sigmap(module), index(module)
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{
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log("Labeling cells.\n");
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discover_nodes(cell_types);
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label_nodes();
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pack_luts();
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log("\n");
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log("Mapping cells.\n");
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map_cells();
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}
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};
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static void split(std::vector<std::string> &tokens, const std::string &text, char sep)
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@ -832,7 +862,7 @@ struct FlowmapPass : public Pass {
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log("be evaluated with the `eval` pass, including cells with multiple output ports\n");
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log("and multi-bit input and output ports.\n");
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log("\n");
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log(" -maxlut <k>\n");
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log(" -maxlut k\n");
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log(" perform technology mapping for a k-LUT architecture. if not specified,\n");
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log(" defaults to 3.\n");
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log("\n");
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@ -846,8 +876,6 @@ struct FlowmapPass : public Pass {
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing FLOWMAP pass (pack LUTs with FlowMap).\n");
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int order = 3;
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vector<string> cells;
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bool debug = false;
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@ -885,18 +913,24 @@ struct FlowmapPass : public Pass {
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cell_types = {"$_NOT_", "$_AND_", "$_OR_", "$_XOR_", "$_MUX_"};
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}
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int mapped_count = 0, packed_count = 0, unique_packed_count = 0;
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log_header(design, "Executing FLOWMAP pass (pack LUTs with FlowMap).\n");
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int gate_count = 0, lut_count = 0, packed_count = 0;
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int gate_area = 0, lut_area = 0;
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for (auto module : design->selected_modules())
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{
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FlowmapWorker worker(order, cell_types, debug, module);
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mapped_count += worker.mapped_count;
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gate_count += worker.gate_count;
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lut_count += worker.lut_count;
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packed_count += worker.packed_count;
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unique_packed_count += worker.unique_packed_count;
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gate_area += worker.gate_area;
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lut_area += worker.lut_area;
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}
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log("\n");
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log("Mapped %d LUTs.\n", mapped_count);
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log("Packed %d cells %d times.\n", unique_packed_count, packed_count);
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log("Mapped %d LUTs.\n", lut_count);
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log("Packed %d cells; duplicated %d cells.\n", packed_count, packed_count - gate_count);
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log("Solution has %.1f%% area overhead.\n", (lut_area - gate_area) * 100.0 / gate_area);
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}
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} FlowmapPass;
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@ -0,0 +1,22 @@
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// Exact reproduction of Figure 2(a) from 10.1109/43.273754.
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module top(...);
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input a,b,c,d,e,f;
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wire nA = b&c;
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wire A = !nA;
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wire nB = c|d;
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wire B = !nB;
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wire nC = e&f;
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wire C = !nC;
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wire D = A|B;
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wire E = a&D;
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wire nF = D&C;
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wire F = !nF;
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wire nG = F|B;
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wire G = !nG;
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wire H = a&F;
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wire I = E|G;
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wire J = G&C;
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wire np = H&I;
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output p = !np;
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output q = A|J;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
// Like flow.v, but results in a network identical to Figure 2(b).
|
||||
module top(...);
|
||||
input a,b,c,d,e,f;
|
||||
wire A = b&c;
|
||||
wire B = c|d;
|
||||
wire C = e&f;
|
||||
wire D = A|B;
|
||||
wire E = a&D;
|
||||
wire F = D&C;
|
||||
wire G = F|B;
|
||||
wire H = a&F;
|
||||
wire I = E|G;
|
||||
wire J = G&C;
|
||||
output p = H&I;
|
||||
output q = A|J;
|
||||
endmodule
|
||||
Loading…
Reference in New Issue