mirror of https://github.com/YosysHQ/yosys.git
flowmap: improve debug graph output. NFC.
This commit is contained in:
whitequark
parent
7850a0c28a
commit
fd21564deb
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@ -64,10 +64,10 @@ PRIVATE_NAMESPACE_BEGIN
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struct GraphStyle
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{
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string label;
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string color;
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string color, fillcolor;
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GraphStyle(string label = "", string color = "black") :
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label(label), color(color) {}
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GraphStyle(string label = "", string color = "black", string fillcolor = "") :
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label(label), color(color), fillcolor(fillcolor) {}
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};
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static string dot_escape(string value)
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@ -110,13 +110,11 @@ static void dump_dot_graph(string filename,
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if (outputs[node])
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shape = "octagon";
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auto prop = node_style(node);
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string id;
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if (node == SigBit())
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id = "(source)";
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else
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id = log_signal(node);
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fprintf(f, " n%d [ shape=%s, fontname=\"Monospace\", label=\"%s%s\", color=\"%s\" ];\n",
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ids[node], shape.c_str(), dot_escape(id).c_str(), dot_escape(prop.label.c_str()).c_str(), prop.color.c_str());
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string style = "";
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if (!prop.fillcolor.empty())
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style = "filled";
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fprintf(f, " n%d [ shape=%s, fontname=\"Monospace\", label=\"%s\", color=\"%s\", fillcolor=\"%s\", style=\"%s\" ];\n",
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ids[node], shape.c_str(), dot_escape(prop.label.c_str()).c_str(), prop.color.c_str(), prop.fillcolor.c_str(), style.c_str());
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}
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fprintf(f, " { rank=\"source\"; ");
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@ -138,8 +136,8 @@ static void dump_dot_graph(string filename,
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if (nodes[source] && nodes[sink])
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{
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auto prop = edge_style(source, sink);
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fprintf(f, " n%d -> n%d [ label=\"%s\", color=\"%s\" ];\n",
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ids[source], ids[sink], dot_escape(prop.label.c_str()).c_str(), prop.color.c_str());
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fprintf(f, " n%d -> n%d [ label=\"%s\", color=\"%s\", fillcolor=\"%s\" ];\n",
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ids[source], ids[sink], dot_escape(prop.label.c_str()).c_str(), prop.color.c_str(), prop.fillcolor.c_str());
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}
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}
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}
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@ -164,7 +162,7 @@ struct FlowGraph
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void dump_dot_graph(string filename)
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{
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auto node_style = [&](RTLIL::SigBit node) {
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string label;
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string label = (node == source) ? "(source)" : log_signal(node);
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for (auto collapsed_node : collapsed[node])
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label += stringf(" %s", log_signal(collapsed_node));
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int flow = node_flow[node];
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@ -423,28 +421,46 @@ struct FlowmapWorker
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int mapped_count = 0, packed_count = 0, unique_packed_count = 0;
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void dump_dot_graph(string filename, pool<RTLIL::SigBit> subgraph = {}, pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> cut = {})
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void dump_dot_graph(string filename,
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pool<RTLIL::SigBit> subgraph_nodes = {}, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> subgraph_edges = {},
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pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> cut = {},
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dict<RTLIL::SigBit, pool<RTLIL::SigBit>> collapsed = {})
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{
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if (subgraph.empty())
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subgraph = nodes;
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if (subgraph_nodes.empty())
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subgraph_nodes = nodes;
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if (subgraph_edges.empty())
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subgraph_edges = edges_fw;
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auto node_style = [&](RTLIL::SigBit node) {
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string label, color;
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string label = log_signal(node);
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for (auto collapsed_node : collapsed[node])
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if (collapsed_node != node)
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label += stringf(" %s", log_signal(collapsed_node));
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if (labels[node] == -1)
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label = string("\n<unlabeled>");
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label += "\nl=?";
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else
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label = stringf("\nl=%d", labels[node]);
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color = "black";
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if (cut.first[node])
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color = "blue";
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if (cut.second[node])
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color = "red";
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return GraphStyle{label, color};
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label += stringf("\nl=%d", labels[node]);
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if (cut.first.empty() && cut.second.empty())
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{
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if (labels[node] == -1)
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return GraphStyle{label};
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string fillcolor = stringf("/set311/%d", 1 + labels[node] % 11);
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return GraphStyle{label, "", fillcolor};
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}
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else
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{
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string color = "black";
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if (cut.first[node])
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color = "blue";
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if (cut.second[node])
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color = "red";
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return GraphStyle{label, color};
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}
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};
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auto edge_style = [&](RTLIL::SigBit, RTLIL::SigBit) {
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return GraphStyle{};
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};
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::dump_dot_graph(filename, subgraph, edges_fw, inputs, outputs, node_style, edge_style, module->name.str());
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::dump_dot_graph(filename, subgraph_nodes, subgraph_edges, inputs, outputs, node_style, edge_style, module->name.str());
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}
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pool<RTLIL::SigBit> find_subgraph(RTLIL::SigBit sink)
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@ -582,8 +598,8 @@ struct FlowmapWorker
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if (debug)
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{
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dump_dot_graph("flowmap-init.dot");
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log("Dumped complete combinatorial graph to `flowmap-init.dot`.\n");
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dump_dot_graph("flowmap-initial.dot");
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log("Dumped complete initial graph to `flowmap-initial.dot`.\n");
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}
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pool<RTLIL::SigBit> worklist = nodes;
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@ -650,7 +666,7 @@ struct FlowmapWorker
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if (debug)
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{
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log(" Maximum flow: %d. Assigned label %d.\n", flow, labels[sink]);
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dump_dot_graph(stringf("flowmap-%d-sub.dot", debug_num), subgraph, {x, xi});
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dump_dot_graph(stringf("flowmap-%d-sub.dot", debug_num), subgraph, {}, {x, xi});
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log(" Dumped subgraph to `flowmap-%d-sub.dot`.\n", debug_num);
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flow_graph.dump_dot_graph(stringf("flowmap-%d-flow.dot", debug_num));
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log(" Dumped flow graph to `flowmap-%d-flow.dot`.\n", debug_num);
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@ -668,17 +684,40 @@ struct FlowmapWorker
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worklist.insert(sink_succ);
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}
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if (debug)
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{
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dump_dot_graph("flowmap-done.dot");
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log("Dumped complete combinatorial graph to `flowmap-done.dot`.\n");
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}
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int depth = 0;
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for (auto label : labels)
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depth = max(depth, label.second);
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log("Maximum depth: %d levels.\n", depth);
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if (debug)
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{
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dump_dot_graph("flowmap-labeled.dot");
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log("Dumped complete labeled graph to `flowmap-labeled.dot`.\n");
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}
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pool<RTLIL::SigBit> lut_nodes;
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dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_edges;
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worklist = outputs;
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while (!worklist.empty())
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{
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auto lut_node = worklist.pop();
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lut_nodes.insert(lut_node);
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for (auto input_node : lut_inputs[lut_node])
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{
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lut_edges[input_node].insert(lut_node);
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if (!lut_nodes[input_node] && !inputs[input_node])
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worklist.insert(input_node);
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}
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}
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if (debug)
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{
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pool<RTLIL::SigBit> lut_and_input_nodes = lut_nodes;
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lut_and_input_nodes.insert(inputs.begin(), inputs.end());
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dump_dot_graph("flowmap-packed.dot", lut_and_input_nodes, lut_edges, {}, lut_gates);
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log("Dumped complete packed graph to `flowmap-packed.dot`.\n");
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}
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ConstEval ce(module);
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for (auto input_node : inputs)
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ce.stop(input_node);
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@ -687,10 +726,8 @@ struct FlowmapWorker
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log("Mapping cells.\n");
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pool<RTLIL::SigBit> mapped_nodes;
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worklist = outputs;
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while (!worklist.empty())
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for (auto node : lut_nodes)
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{
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auto node = worklist.pop();
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if (node_origins.count(node))
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{
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auto origin = node_origins[node];
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@ -750,22 +787,14 @@ struct FlowmapWorker
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RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table);
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mapped_count++;
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mapped_nodes.insert(node);
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for (auto gate_node : lut_gates[node])
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{
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auto gate_origin = node_origins[gate_node];
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lut->add_strpool_attribute("\\src", gate_origin.cell->get_strpool_attribute("\\src"));
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packed_count++;
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}
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log(" Packed into a %d-LUT %s.%s.\n", (int)input_nodes.size(), log_id(module), log_id(lut));
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mapped_nodes.insert(node);
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for (auto input_node : input_nodes)
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{
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if (!mapped_nodes[input_node] && !inputs[input_node])
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worklist.insert(input_node);
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}
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}
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unique_packed_count += nodes.size();
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