mirror of https://github.com/YosysHQ/yosys.git
Fixed a bug in opt_const when optimizing 1-bit compares with constants
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@ -181,8 +181,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module)
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RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
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if (a.is_fully_const()) {
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RTLIL::SigSpec tmp = a;
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a = b, b = tmp;
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RTLIL::SigSpec tmp;
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tmp = a, a = b, b = tmp;
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cell->connections["\\A"] = a;
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cell->connections["\\B"] = b;
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}
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if (b.is_fully_const()) {
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