mirror of https://github.com/YosysHQ/yosys.git
Added DFFE support to "abc" pass
This commit is contained in:
Clifford Wolf
parent
5df192e71c
commit
f7b323196f
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@ -95,8 +95,8 @@ RTLIL::Module *module;
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std::vector<gate_t> signal_list;
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std::map<RTLIL::SigBit, int> signal_map;
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bool clk_polarity;
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RTLIL::SigSpec clk_sig;
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bool clk_polarity, en_polarity;
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RTLIL::SigSpec clk_sig, en_sig;
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int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1)
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{
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@ -147,7 +147,24 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
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return;
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if (clk_sig != assign_map(cell->getPort("\\C")))
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return;
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goto matching_dff;
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}
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if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
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{
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if (clk_polarity != (cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_"))
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return;
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if (en_polarity != (cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_"))
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return;
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if (clk_sig != assign_map(cell->getPort("\\C")))
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return;
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if (en_sig != assign_map(cell->getPort("\\E")))
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return;
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goto matching_dff;
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}
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if (0) {
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matching_dff:
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RTLIL::SigSpec sig_d = cell->getPort("\\D");
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RTLIL::SigSpec sig_q = cell->getPort("\\Q");
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@ -556,6 +573,9 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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clk_polarity = true;
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clk_sig = RTLIL::SigSpec();
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en_polarity = true;
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en_sig = RTLIL::SigSpec();
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std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
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if (!cleanup)
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tempdir_name[0] = tempdir_name[4] = '_';
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@ -607,6 +627,17 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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fclose(f);
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if (clk_str.empty()) {
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if (clk_str.find(',') != std::string::npos) {
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int pos = clk_str.find(',');
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std::string en_str = clk_str.substr(pos+1);
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clk_str = clk_str.substr(0, pos);
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if (en_str[0] == '!') {
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en_polarity = false;
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en_str = en_str.substr(1);
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}
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if (module->wires_.count(RTLIL::escape_id(en_str)) != 0)
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en_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(en_str)), 0));
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}
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if (clk_str[0] == '!') {
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clk_polarity = false;
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clk_str = clk_str.substr(1);
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@ -618,19 +649,34 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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if (dff_mode && clk_sig.size() == 0)
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{
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int best_dff_counter = 0;
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std::map<std::pair<bool, RTLIL::SigSpec>, int> dff_counters;
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typedef std::tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
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std::map<clkdomain_t, int> dff_counters;
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for (auto &it : module->cells_)
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{
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RTLIL::Cell *cell = it.second;
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if (cell->type != "$_DFF_N_" && cell->type != "$_DFF_P_")
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clkdomain_t key;
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if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
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{
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key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
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}
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else
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if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
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{
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bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
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bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
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key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
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}
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else
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continue;
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std::pair<bool, RTLIL::SigSpec> key(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")));
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if (++dff_counters[key] > best_dff_counter) {
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best_dff_counter = dff_counters[key];
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clk_polarity = key.first;
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clk_sig = key.second;
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clk_polarity = std::get<0>(key);
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clk_sig = std::get<1>(key);
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en_polarity = std::get<2>(key);
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en_sig = std::get<3>(key);
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}
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}
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}
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@ -638,13 +684,20 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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if (dff_mode || !clk_str.empty()) {
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if (clk_sig.size() == 0)
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log("No (matching) clock domain found. Not extracting any FF cells.\n");
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else
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log("Found (matching) %s clock domain: %s\n", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig));
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else {
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log("Found (matching) %s clock domain: %s", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig));
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if (en_sig.size() != 0)
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log(", enabled by %s%s", en_polarity ? "" : "!", log_signal(en_sig));
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log("\n");
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}
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}
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if (clk_sig.size() != 0)
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mark_port(clk_sig);
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if (en_sig.size() != 0)
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mark_port(en_sig);
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std::vector<RTLIL::Cell*> cells;
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cells.reserve(module->cells_.size());
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for (auto &it : module->cells_)
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@ -899,7 +952,14 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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}
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if (c->type == "\\DFF") {
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log_assert(clk_sig.size() == 1);
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RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
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RTLIL::Cell *cell;
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if (en_sig.size() == 0) {
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cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
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} else {
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log_assert(en_sig.size() == 1);
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cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
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cell->setPort("\\E", en_sig);
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}
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cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
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cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
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cell->setPort("\\C", clk_sig);
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@ -924,7 +984,14 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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}
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if (c->type == "\\_dff_") {
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log_assert(clk_sig.size() == 1);
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RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
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RTLIL::Cell *cell;
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if (en_sig.size() == 0) {
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cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
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} else {
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log_assert(en_sig.size() == 1);
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cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
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cell->setPort("\\E", en_sig);
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}
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cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
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cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
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cell->setPort("\\C", clk_sig);
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