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Merge pull request #48 from rubund/master 

Fixed typos found by lintian
This commit is contained in:
Clifford Wolf 2015-02-01 22:55:52 +01:00
parent 893fe87a33 49649d6ef0
commit 6eb34038f4
2 changed files with 3 additions and 3 deletions
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2
passes/abc/abc.cc
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@ -1174,7 +1174,7 @@ struct AbcPass : public Pass {
log(" -markgroups\n");
log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
log(" this attribute is a unique integer for each ABC process started. This\n");
log(" is usefull for debugging the partitioning of clock domains.\n");
log(" is useful for debugging the partitioning of clock domains.\n");
log("\n");
log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
log("loaded into ABC before the ABC script is executed.\n");

4
passes/memory/memory_bram.cc
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@ -1110,7 +1110,7 @@ struct MemoryBramPass : public Pass {
log("It is possible to match against the following values with min/max rules:\n");
log("\n");
log(" words ........ number of words in memory in design\n");
log(" abits ........ number of adress bits on memory in design\n");
log(" abits ........ number of address bits on memory in design\n");
log(" dbits ........ number of data bits on memory in design\n");
log(" wports ....... number of write ports on memory in design\n");
log(" rports ....... number of read ports on memory in design\n");
@ -1137,7 +1137,7 @@ struct MemoryBramPass : public Pass {
log("the next also has 'or_next_if_better' set, and so forth).\n");
log("\n");
log("A match containing the command 'make_transp' will add external circuitry\n");
log("to simulate 'transparent read', if neccessary.\n");
log("to simulate 'transparent read', if necessary.\n");
log("\n");
log("A match containing the command 'shuffle_enable A' will re-organize\n");
log("the data bits to accommodate the enable pattern of port A.\n");