mirror of https://github.com/YosysHQ/yosys.git
Temporarily derive blackbox modules in hierarchy to evaluate port widths
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -620,6 +620,8 @@ struct HierarchyPass : public Pass {
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}
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}
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std::set<Module*> blackbox_derivatives;
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for (auto module : design->modules())
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for (auto cell : module->cells())
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{
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@ -628,9 +630,17 @@ struct HierarchyPass : public Pass {
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Module *m = design->module(cell->type);
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if (m == nullptr || m->get_bool_attribute("\\blackbox"))
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if (m == nullptr)
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continue;
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if (m->get_bool_attribute("\\blackbox") && cell->parameters.size()) {
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IdString new_m_name = m->derive(design, cell->parameters);
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if (new_m_name != m->name) {
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m = design->module(new_m_name);
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blackbox_derivatives.insert(m);
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}
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}
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for (auto &conn : cell->connections())
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{
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Wire *w = m->wire(conn.first);
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@ -673,6 +683,9 @@ struct HierarchyPass : public Pass {
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}
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}
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for (auto module : blackbox_derivatives)
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design->remove(module);
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log_pop();
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}
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} HierarchyPass;
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