mirror of https://github.com/YosysHQ/yosys.git
Less aggressive "share" defaults
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4f68a77e3f
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87819c62fa
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@ -369,7 +369,9 @@ struct ShareWorker
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}
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if (cell->type == "$memrd") {
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if (!cell->parameters.at("\\CLK_ENABLE").as_bool())
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if (cell->parameters.at("\\CLK_ENABLE").as_bool())
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continue;
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if (config.opt_aggressive || !modwalker.sigmap(cell->getPort("\\ADDR")).is_fully_const())
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shareable_cells.insert(cell);
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continue;
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}
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@ -387,7 +389,7 @@ struct ShareWorker
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}
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if (generic_ops.count(cell->type)) {
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 10)
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if (config.opt_aggressive)
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shareable_cells.insert(cell);
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continue;
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}
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@ -1105,7 +1107,7 @@ struct ShareWorker
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RTLIL::Cell *cell = *shareable_cells.begin();
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shareable_cells.erase(cell);
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log(" Analyzing resource sharing options for %s:\n", log_id(cell));
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log(" Analyzing resource sharing options for %s (%s):\n", log_id(cell), log_id(cell->type));
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const pool<ssc_pair_t> &cell_activation_patterns = find_cell_activation_patterns(cell, " ");
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RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns);
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@ -1138,7 +1140,7 @@ struct ShareWorker
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for (auto other_cell : candidates)
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{
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log(" Analyzing resource sharing with %s:\n", log_id(other_cell));
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log(" Analyzing resource sharing with %s (%s):\n", log_id(other_cell), log_id(other_cell->type));
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const pool<ssc_pair_t> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell, " ");
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RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns);
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