mirror of https://github.com/YosysHQ/yosys.git
Improved read_verilog support for empty behavioral statements
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@ -946,7 +946,7 @@ simple_behavioral_stmt:
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// this production creates the obligatory if-else shift/reduce conflict
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behavioral_stmt:
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defattr | assert | wire_decl |
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simple_behavioral_stmt ';' |
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simple_behavioral_stmt ';' | ';' |
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hierarchical_id attr {
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AstNode *node = new AstNode(AST_TCALL);
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node->str = *$1;
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@ -1060,10 +1060,6 @@ opt_synopsys_attr:
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} |
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/* empty */;
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behavioral_stmt_opt:
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behavioral_stmt |
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';' ;
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behavioral_stmt_list:
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behavioral_stmt_list behavioral_stmt |
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/* empty */;
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@ -1092,7 +1088,7 @@ case_item:
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ast_stack.back()->children.push_back(block);
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ast_stack.push_back(block);
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case_type_stack.push_back(0);
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} behavioral_stmt_opt {
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} behavioral_stmt {
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case_type_stack.pop_back();
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ast_stack.pop_back();
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ast_stack.pop_back();
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