mirror of https://github.com/YosysHQ/yosys.git
recover_reduce_core: Initial commit
Conflicts: passes/techmap/Makefile.inc
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@ -17,6 +17,7 @@ OBJS += passes/techmap/iopadmap.o
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OBJS += passes/techmap/hilomap.o
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OBJS += passes/techmap/extract.o
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OBJS += passes/techmap/extract_fa.o
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OBJS += passes/techmap/recover_reduce_core.o
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OBJS += passes/techmap/alumacc.o
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OBJS += passes/techmap/dff2dffe.o
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OBJS += passes/techmap/dffinit.o
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@ -0,0 +1,109 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2017 Robert Ou <rqou@robertou.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct RecoverReduceCorePass : public Pass {
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enum GateType {
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And,
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Or,
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Xor
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};
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RecoverReduceCorePass() : Pass("recover_reduce_core", "converts gate chains into $reduce_*") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" recover_reduce_core\n");
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log("\n");
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log("converts gate chains into $reduce_*\n");
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log("\n");
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log("This performs the core step of the recover_reduce command. This step recognizes\n");
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log("chains of gates found by the previous steps and converts these chains into one\n");
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log("logical cell.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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(void)args;
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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// Index all of the nets in the module
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dict<SigBit, Cell*> sig_to_driver;
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dict<SigBit, pool<Cell*>> sig_to_sink;
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for (auto cell : module->selected_cells())
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{
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for (auto &conn : cell->connections())
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{
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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sig_to_driver[bit] = cell;
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if (cell->input(conn.first))
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{
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for (auto bit : sigmap(conn.second))
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{
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if (sig_to_sink.count(bit) == 0)
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sig_to_sink[bit] = pool<Cell*>();
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sig_to_sink[bit].insert(cell);
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}
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}
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}
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}
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// Need to check if any wires connect to module ports
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pool<SigBit> port_sigs;
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for (auto wire : module->selected_wires())
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if (wire->port_input || wire->port_output)
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for (auto bit : sigmap(wire))
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port_sigs.insert(bit);
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// Actual logic starts here
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pool<Cell*> consumed_cells;
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for (auto cell : module->selected_cells())
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{
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if (consumed_cells.count(cell))
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continue;
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GateType gt;
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if (cell->type == "$_AND_")
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gt = GateType::And;
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else if (cell->type == "$_OR_")
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gt = GateType::Or;
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else if (cell->type == "$_XOR_")
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gt = GateType::Xor;
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else
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continue;
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log("Working on cell %s...\n", cell->name.c_str());
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}
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}
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}
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} RecoverReduceCorePass;
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PRIVATE_NAMESPACE_END
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