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added log_header to miter and expose pass, show cell type for exposed ports

This commit is contained in:
Johann Glaser 2014-05-28 18:05:38 +02:00
parent 63dfbb18cf
commit 278085fa01
2 changed files with 9 additions and 3 deletions
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8
passes/sat/expose.cc
View File

@ -259,6 +259,8 @@ struct ExposePass : public Pass {
bool flag_evert_dff = false;
std::string sep = ".";
log_header("Executing EXPOSE pass (exposing internal signals as outputs).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
@ -629,7 +631,7 @@ struct ExposePass : public Pass {
w->port_input = true;
add_new_wire(module, w);
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
RTLIL::SigSpec sig;
if (cell->connections.count(p->name) != 0)
@ -654,7 +656,7 @@ struct ExposePass : public Pass {
w->port_input = true;
add_new_wire(module, w);
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
if (w->port_input)
module->connections.push_back(RTLIL::SigSig(it.second, w));
@ -667,7 +669,7 @@ struct ExposePass : public Pass {
}
for (auto &it : delete_cells) {
log("Removing cell: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it));
log("Removing cell: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it), RTLIL::id2cstr(module->cells.at(it)->type));
delete module->cells.at(it);
module->cells.erase(it);
}

4
passes/sat/miter.cc
View File

@ -28,6 +28,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
bool flag_make_outcmp = false;
bool flag_make_assert = false;
log_header("Executing MITER pass (creating miter circuit).\n");
size_t argidx;
for (argidx = 2; argidx < args.size(); argidx++)
{
@ -102,6 +104,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
log_cmd_error("No matching port in gold module was found for %s!\n", it.second->name.c_str());
}
log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name));
RTLIL::Module *miter_module = new RTLIL::Module;
miter_module->name = miter_name;
design->modules[miter_name] = miter_module;