mirror of https://github.com/YosysHQ/yosys.git
Add "sim" command skeleton
This commit is contained in:
Clifford Wolf
parent
e9918365fd
commit
75046aa531
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@ -2,6 +2,7 @@
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OBJS += passes/sat/sat.o
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OBJS += passes/sat/freduce.o
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OBJS += passes/sat/eval.o
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OBJS += passes/sat/sim.o
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OBJS += passes/sat/miter.o
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OBJS += passes/sat/expose.o
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OBJS += passes/sat/assertpmux.o
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@ -0,0 +1,371 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SimInstance
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{
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Module *module;
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Cell *instance;
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SimInstance *parent;
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dict<Cell*, SimInstance*> children;
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SigMap sigmap;
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dict<SigBit, State> state_nets;
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dict<SigBit, pool<Cell*>> upd_cells;
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dict<SigBit, pool<Wire*>> upd_outports;
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pool<SigBit> dirty_bits;
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dict<SigBit, State> next_state_nets;
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dict<Wire*, int> vcd_netids;
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SimInstance(Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
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module(module), instance(instance), parent(parent), sigmap(module)
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{
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if (parent) {
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log_assert(parent->children.count(instance) == 0);
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parent->children[instance] = this;
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}
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for (auto wire : module->wires())
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{
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SigSpec sig = sigmap(wire);
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for (int i = 0; i < GetSize(sig); i++) {
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if (state_nets.count(sig[i]) == 0)
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state_nets[sig[i]] = State::Sx;
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if (wire->port_output) {
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upd_outports[sig[i]].insert(wire);
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dirty_bits.insert(sig[i]);
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}
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}
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if (wire->attributes.count("\\init")) {
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Const initval = wire->attributes.at("\\init");
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for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
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if (initval[i] == State::S0 || initval[i] == State::S1) {
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state_nets[sig[i]] = initval[i];
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dirty_bits.insert(sig[i]);
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}
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}
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}
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for (auto cell : module->cells())
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{
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Module *mod = module->design->module(cell->type);
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if (mod != nullptr) {
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new SimInstance(mod, cell, this);
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}
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for (auto &port : cell->connections()) {
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if (cell->input(port.first))
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for (auto bit : sigmap(port.second))
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upd_cells[bit].insert(cell);
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}
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}
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}
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IdString name() const
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{
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if (instance != nullptr)
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return instance->name;
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return module->name;
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}
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std::string hiername() const
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{
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if (instance != nullptr)
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return parent->hiername() + "." + log_id(instance->name);
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return log_id(module->name);
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}
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Const get_state(SigSpec sig)
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{
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Const value;
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for (auto bit : sigmap(sig))
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if (state_nets.count(bit))
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value.bits.push_back(state_nets.at(bit));
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else
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value.bits.push_back(State::Sz);
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// log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
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return value;
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}
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void set_state(SigSpec sig, Const value)
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{
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sig = sigmap(sig);
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log_assert(GetSize(sig) == GetSize(value));
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for (int i = 0; i < GetSize(sig); i++)
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if (state_nets.at(sig[i]) != value[i]) {
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state_nets.at(sig[i]) = value[i];
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dirty_bits.insert(sig[i]);
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}
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// log("[%s] set %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
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}
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void update_cell(Cell *cell)
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{
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if (children.count(cell))
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{
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auto child = children.at(cell);
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for (auto &conn: cell->connections())
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if (cell->input(conn.first)) {
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Const value = get_state(conn.second);
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child->set_state(child->module->wire(conn.first), value);
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}
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return;
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}
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if (yosys_celltypes.cell_evaluable(cell->type))
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{
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// log("[%s] eval %s (%s)\n", hiername().c_str(), log_id(cell), log_id(cell->type));
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RTLIL::SigSpec sig_a, sig_b, sig_c, sig_d, sig_s, sig_y;
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bool has_a, has_b, has_c, has_d, has_s, has_y;
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has_a = cell->hasPort("\\A");
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has_b = cell->hasPort("\\B");
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has_c = cell->hasPort("\\C");
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has_d = cell->hasPort("\\D");
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has_s = cell->hasPort("\\S");
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has_y = cell->hasPort("\\Y");
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if (has_a) sig_a = cell->getPort("\\A");
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if (has_b) sig_b = cell->getPort("\\B");
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if (has_c) sig_c = cell->getPort("\\C");
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if (has_d) sig_d = cell->getPort("\\D");
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if (has_s) sig_s = cell->getPort("\\S");
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if (has_y) sig_y = cell->getPort("\\Y");
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// Simple (A -> Y) and (A,B -> Y) cells
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if (has_a && !has_c && !has_d && !has_s && has_y) {
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set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b)));
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return;
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}
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// (A,B,C -> Y) cells
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if (has_a && has_b && has_c && !has_d && !has_s && has_y) {
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set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_c)));
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return;
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}
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// (A,B,S -> Y) cells
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if (has_a && has_b && !has_c && !has_d && has_s && has_y) {
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set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_s)));
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return;
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}
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log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
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return;
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}
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// FIXME
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log_warning("Unsupported cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
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}
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void update()
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{
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while (1)
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{
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while (!dirty_bits.empty())
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{
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SigBit bit = *dirty_bits.begin();
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dirty_bits.erase(bit);
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if (upd_cells.count(bit))
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{
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for (auto cell : upd_cells.at(bit))
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update_cell(cell);
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}
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if (upd_outports.count(bit) && parent != nullptr)
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{
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for (auto wire : upd_outports.at(bit))
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if (instance->hasPort(wire->name)) {
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Const value = get_state(wire);
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parent->set_state(instance->getPort(wire->name), value);
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}
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}
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}
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for (auto child : children)
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child.second->update();
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if (dirty_bits.empty())
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break;
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}
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}
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void write_vcd_header(std::ofstream &f, int &id)
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{
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f << stringf("$scope module %s $end\n", log_id(name()));
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for (auto wire : module->wires())
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{
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if (wire->name[0] == '$')
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continue;
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f << stringf("$var wire %d n%d %s $end\n", GetSize(wire), id, log_id(wire));
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vcd_netids[wire] = id++;
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}
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for (auto child : children)
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child.second->write_vcd_header(f, id);
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f << stringf("$upscope $end\n");
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}
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void write_vcd_step(std::ofstream &f)
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{
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for (auto it : vcd_netids)
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{
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Wire *wire = it.first;
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Const value = get_state(wire);
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int id = it.second;
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f << "b";
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for (int i = GetSize(value)-1; i >= 0; i--) {
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switch (value[i]) {
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case State::S0: f << "0"; break;
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case State::S1: f << "1"; break;
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case State::Sx: f << "x"; break;
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default: f << "z";
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}
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}
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f << stringf(" n%d\n", id);
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}
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for (auto child : children)
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child.second->write_vcd_step(f);
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}
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};
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struct SimWorker
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{
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SimInstance *top = nullptr;
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std::ofstream vcdfile;
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void initialize(Module *topmod)
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{
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top = new SimInstance(topmod);
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top->update();
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}
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void step()
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{
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// FIXME
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}
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void write_vcd_header()
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{
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if (!vcdfile.is_open())
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return;
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int id = 1;
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top->write_vcd_header(vcdfile, id);
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vcdfile << stringf("$enddefinitions $end\n");
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}
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void write_vcd_step(int n)
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{
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if (!vcdfile.is_open())
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return;
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vcdfile << stringf("#%d\n", 10*n);
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top->write_vcd_step(vcdfile);
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}
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};
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struct SimPass : public Pass {
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SimPass() : Pass("sim", "simulate the circuit") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" sim [options] [top-level]\n");
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log("\n");
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log("This command simulates the circuit using the given top-level module.\n");
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log("\n");
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log(" -vcd <filename>\n");
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log(" write the simulation results to the given VCD file\n");
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log("\n");
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log(" -n <integer>\n");
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log(" number of steps to simulate (default: 20)\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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SimWorker worker;
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int numsteps = 20;
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log_header(design, "Executing SIM pass (simulate the circuit).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-vcd" && argidx+1 < args.size()) {
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worker.vcdfile.open(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-n" && argidx+1 < args.size()) {
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numsteps = atoi(args[++argidx].c_str());
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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Module *top_mod = nullptr;
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if (design->full_selection()) {
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top_mod = design->top_module();
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} else {
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auto mods = design->selected_whole_modules();
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if (GetSize(mods) != 1)
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log_cmd_error("Only one top module must be selected.\n");
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top_mod = mods.front();
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}
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worker.initialize(top_mod);
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worker.write_vcd_header();
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worker.write_vcd_step(0);
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for (int i = 1; i < numsteps; i++) {
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worker.step();
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worker.write_vcd_step(i);
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}
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}
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} SimPass;
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PRIVATE_NAMESPACE_END
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