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Merge remote-tracking branch 'origin/eddie/split_shiftx' into xc7mux

This commit is contained in:
Eddie Hung 2019-04-25 18:52:20 -07:00
parent 3042d58330 ece2c49e92
commit 880652283c
4 changed files with 157 additions and 16 deletions
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7
passes/pmgen/split_shiftx.cc
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@ -26,9 +26,9 @@ PRIVATE_NAMESPACE_BEGIN
void create_split_shiftx(split_shiftx_pm &pm)
{
if (pm.st.shiftxB.empty())
return;
log_assert(pm.st.shiftx);
if (pm.blacklist_cells.count(pm.st.shiftx))
return;
SigSpec A = pm.st.shiftx->getPort("\\A");
SigSpec Y = pm.st.shiftx->getPort("\\Y");
const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int();
@ -56,7 +56,8 @@ struct BitblastShiftxPass : public Pass {
log(" split_shiftx [selection]\n");
log("\n");
log("Split up $shiftx cells where Y_WIDTH > 1, with consideration for any $macc\n");
log("cells that may be driving their B inputs.\n");
log("cells -- configured as a constant multiplier equal to Y_WIDTH -- that may be\n");
log("driving their B inputs.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE

27
passes/pmgen/split_shiftx.pmg
View File

@ -5,50 +5,51 @@ match shiftx
select param(shiftx, \Y_WIDTH).as_int() > 1
endmatch
code shiftxB
shiftxB = port(shiftx, \B);
const int b_width = param(shiftx, \B_WIDTH).as_int();
if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0)
shiftxB = shiftxB.extract(0, b_width-1);
endcode
match macc
select macc->type == $macc
select param(macc, \B_WIDTH).as_int() == 0
index <SigSpec> port(macc, \Y) === shiftxB
optional
endmatch
code shiftxB
if (macc) {
shiftxB = port(shiftx, \B);
const int b_width = param(shiftx, \B_WIDTH).as_int();
if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0)
shiftxB = shiftxB.extract(0, b_width-1);
if (port(macc, \Y) != shiftxB) {
blacklist(shiftx);
reject;
}
Const config = param(macc, \CONFIG);
const int config_width = param(macc, \CONFIG_WIDTH).as_int();
const int num_bits = config.extract(0, 4).as_int();
const int num_ports = (config_width - 4) / (2 + 2*num_bits);
if (num_ports != 1) {
shiftxB = nullptr;
blacklist(shiftx);
reject;
}
// IS_SIGNED?
if (config[4] == 1) {
shiftxB = nullptr;
blacklist(shiftx);
reject;
}
// DO_SUBTRACT?
if (config[5] == 1) {
shiftxB = nullptr;
blacklist(shiftx);
reject;
}
const int port_size_A = config.extract(6, num_bits).as_int();
const int port_size_B = config.extract(6 + num_bits, num_bits).as_int();
const SigSpec port_B = port(macc, \A).extract(port_size_A, port_size_B);
if (!port_B.is_fully_const()) {
shiftxB = nullptr;
blacklist(shiftx);
reject;
}
const int multiply_factor = port_B.as_int();
if (multiply_factor != param(shiftx, \Y_WIDTH).as_int()) {
shiftxB = nullptr;
blacklist(shiftx);
reject;
}
shiftxB = port(macc, \A).extract(0, port_size_A);

118
tests/various/split_shiftx.v Normal file
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@ -0,0 +1,118 @@
module split_shiftx_test01(i, s, o);
wire [3:0] _0_;
input [8:0] i;
output [2:0] o;
input [1:0] s;
\$macc #(
.A_WIDTH(32'd4),
.B_WIDTH(32'd0),
.CONFIG(10'h282),
.CONFIG_WIDTH(32'd10),
.Y_WIDTH(32'd4)
) _1_ (
.A({ 2'h3, s }),
.B(),
.Y(_0_)
);
\$shiftx #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd9),
.B_SIGNED(32'd1),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd3)
) _2_ (
.A(i),
.B({ 1'h0, _0_ }),
.Y(o)
);
endmodule
// Sign bit is 1
module split_shiftx_test02(i, s, o);
wire [3:0] _0_;
input [8:0] i;
output [2:0] o;
input [1:0] s;
\$macc #(
.A_WIDTH(32'd4),
.B_WIDTH(32'd0),
.CONFIG(10'h282),
.CONFIG_WIDTH(32'd10),
.Y_WIDTH(32'd4)
) _1_ (
.A({ 2'h3, s }),
.B(),
.Y(_0_)
);
\$shiftx #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd9),
.B_SIGNED(32'd1),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd3)
) _2_ (
.A(i),
.B({ 1'h1, _0_ }),
.Y(o)
);
endmodule
// Non constant $macc
module split_shiftx_test03(i, s, o);
wire [3:0] _0_;
input [8:0] i;
output [2:0] o;
input [1:0] s;
\$macc #(
.A_WIDTH(32'd4),
.B_WIDTH(32'd0),
.CONFIG(10'h282),
.CONFIG_WIDTH(32'd10),
.Y_WIDTH(32'd4)
) _1_ (
.A({ s, s }),
.B(),
.Y(_0_)
);
\$shiftx #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd9),
.B_SIGNED(32'd1),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd3)
) _2_ (
.A(i),
.B({ 1'h0, _0_ }),
.Y(o)
);
endmodule
// Wrong constant $macc
module split_shiftx_test04(i, s, o);
wire [3:0] _0_;
input [8:0] i;
output [2:0] o;
input [1:0] s;
\$macc #(
.A_WIDTH(32'd4),
.B_WIDTH(32'd0),
.CONFIG(10'h282),
.CONFIG_WIDTH(32'd10),
.Y_WIDTH(32'd4)
) _1_ (
.A({ 2'h2, s }),
.B(),
.Y(_0_)
);
\$shiftx #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd9),
.B_SIGNED(32'd1),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd3)
) _2_ (
.A(i),
.B({ 1'h0, _0_ }),
.Y(o)
);
endmodule

21
tests/various/split_shiftx.ys Normal file
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@ -0,0 +1,21 @@
read_verilog -icells split_shiftx.v
split_shiftx
cd split_shiftx_test01
select -assert-count 3 t:$shiftx
select -assert-count 0 t: t:$shiftx %n %i
cd split_shiftx_test02
select -assert-count 1 t:$shiftx
select -assert-count 1 t:$macc
select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
cd split_shiftx_test03
select -assert-count 1 t:$shiftx
select -assert-count 1 t:$macc
select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
cd split_shiftx_test04
select -assert-count 1 t:$shiftx
select -assert-count 1 t:$macc
select -assert-count 0 t: t:$shiftx t:$macc %u %n %i