riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #720 from whitequark/master 

lut2mux: handle 1-bit INIT constant in $lut cells
This commit is contained in:
Clifford Wolf 2018-12-16 15:27:23 +01:00 committed by GitHub
parent 0b9bb852c6 d1f2cb01dc
commit 556341a77f
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
passes/opt/opt_lut.cc
View File

@ -58,7 +58,7 @@ struct OptLutWorker
}
}
return lut_table.extract(lut_index).as_int();
return lut_table.extract(lut_index).as_bool();
}
void show_stats_by_arity()

2
passes/techmap/lut2mux.cc
View File

@ -32,7 +32,7 @@ int lut2mux(Cell *cell)
if (GetSize(sig_a) == 1)
{
cell->module->addMuxGate(NEW_ID, lut[0], lut[1], sig_a, sig_y);
cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y);
}
else
{