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Fix handling of empty cell port assignments (i.e. ignore them)

This commit is contained in:
Clifford Wolf 2017-07-21 19:32:31 +02:00
parent 36cf18ac4c
commit b3bc7068d1
2 changed files with 6 additions and 0 deletions
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3
passes/hierarchy/hierarchy.cc
View File

@ -640,6 +640,9 @@ struct HierarchyPass : public Pass {
if (w == nullptr || w->port_id == 0)
continue;
if (GetSize(conn.second) == 0)
continue;
if (GetSize(w) == GetSize(conn.second))
continue;

3
passes/techmap/techmap.cc
View File

@ -247,6 +247,9 @@ struct TechmapWorker
continue;
}
if (GetSize(it.second) == 0)
continue;
RTLIL::Wire *w = tpl->wires_.at(portname);
RTLIL::SigSig c, extra_connect;