mirror of https://github.com/YosysHQ/yosys.git
Add "stat -tech cmos"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -223,6 +223,33 @@ struct statdata_t
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log("\n");
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log(" Estimated number of LCs: %10d\n", lc_cnt);
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}
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if (tech == "cmos")
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{
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int tran_cnt = 0;
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bool tran_cnt_exact = true;
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for (auto it : num_cells_by_type) {
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auto ctype = it.first;
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auto cnum = it.second;
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if (ctype == "$_NOT_")
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tran_cnt += 2*cnum;
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else if (ctype.in("$_NAND_", "$_NOR_"))
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tran_cnt += 4*cnum;
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else if (ctype.in("$_AOI3_", "$_OAI3_"))
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tran_cnt += 6*cnum;
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else if (ctype.in("$_AOI4_", "$_OAI4_"))
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tran_cnt += 8*cnum;
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else if (ctype.in("$_DFF_P_", "$_DFF_N_"))
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tran_cnt += 16*cnum;
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else
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tran_cnt_exact = false;
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}
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log("\n");
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log(" Estimated number of transistors: %10d%s\n", tran_cnt, tran_cnt_exact ? "" : "+");
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}
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}
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};
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@ -286,7 +313,7 @@ struct StatPass : public Pass {
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log("\n");
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log(" -tech <technology>\n");
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log(" print area estemate for the specified technology. Currently supported\n");
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log(" values for <technology>: xilinx\n");
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log(" values for <technology>: xilinx, cmos\n");
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log("\n");
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log(" -width\n");
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log(" annotate internal cell types with their word width.\n");
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@ -330,7 +357,7 @@ struct StatPass : public Pass {
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}
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extra_args(args, argidx, design);
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if (techname != "" && techname != "xilinx")
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if (techname != "" && techname != "xilinx" && techname != "cmos")
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log_cmd_error("Unsupported technology: '%s'\n", techname.c_str());
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for (auto mod : design->selected_modules())
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