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Merge pull request #1208 from ZirconiumX/intel_cleanups 

Assorted synth_intel cleanups from @bwidawsk
This commit is contained in:
David Shah 2019-07-18 19:04:28 +01:00 committed by GitHub
parent 8e0f7c18f1 0c999ac2c4
commit 9cb0456b6f
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 14 additions and 29 deletions
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43
techlibs/intel/synth_intel.cc
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@ -38,9 +38,9 @@ struct SynthIntelPass : public ScriptPass {
log("\n");
log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
log(" generate the synthesis netlist for the specified family.\n");
log(" MAX10 is the default target if not family argument specified.\n");
log(" MAX10 is the default target if no family argument specified.\n");
log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
log(" Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n");
log(" Cyclone V and Arria 10 GX devices are experimental.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module (default='top')\n");
@ -147,9 +147,13 @@ struct SynthIntelPass : public ScriptPass {
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
if (family_opt != "max10" && family_opt != "a10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" &&
family_opt != "cycloneive" && family_opt != "cyclone10")
log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
if (family_opt != "max10" &&
family_opt != "a10gx" &&
family_opt != "cyclonev" &&
family_opt != "cycloneiv" &&
family_opt != "cycloneive" &&
family_opt != "cyclone10")
log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str());
log_header(design, "Executing SYNTH_INTEL pass.\n");
log_push();
@ -162,18 +166,9 @@ struct SynthIntelPass : public ScriptPass {
void script() YS_OVERRIDE
{
if (check_label("begin")) {
if (check_label("family") && family_opt == "max10")
run("read_verilog -sv -lib +/intel/max10/cells_sim.v");
else if (check_label("family") && family_opt == "a10gx")
run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
else if (check_label("family") && family_opt == "cyclonev")
run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
else if (check_label("family") && family_opt == "cyclone10")
run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
else if (check_label("family") && family_opt == "cycloneiv")
run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
else
run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
if (check_label("family"))
run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
// Misc and common cells
run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
@ -222,18 +217,8 @@ struct SynthIntelPass : public ScriptPass {
if (check_label("map_cells")) {
if (!noiopads)
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
if (family_opt == "max10")
run("techmap -map +/intel/max10/cells_map.v");
else if (family_opt == "a10gx")
run("techmap -map +/intel/a10gx/cells_map.v");
else if (family_opt == "cyclonev")
run("techmap -map +/intel/cyclonev/cells_map.v");
else if (family_opt == "cyclone10")
run("techmap -map +/intel/cyclone10/cells_map.v");
else if (family_opt == "cycloneiv")
run("techmap -map +/intel/cycloneiv/cells_map.v");
else
run("techmap -map +/intel/cycloneive/cells_map.v");
run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
run("dffinit -highlow -ff dffeas q power_up");
run("clean -purge");
}