From 060e77c09b51aabe712315d5fd655f62a765d62f Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Mon, 8 Jul 2019 12:03:00 -0700 Subject: [PATCH 1/7] intel_synth: Minor code cleanups Signed-off-by: Ben Widawsky --- techlibs/intel/synth_intel.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 09c9ba3af..69f3b6334 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -147,8 +147,12 @@ struct SynthIntelPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); - if (family_opt != "max10" && family_opt != "a10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" && - family_opt != "cycloneive" && family_opt != "cyclone10") + if (family_opt != "max10" && + family_opt != "a10gx" && + family_opt != "cyclonev" && + family_opt != "cycloneiv" && + family_opt != "cycloneive" && + family_opt != "cyclone10") log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str()); log_header(design, "Executing SYNTH_INTEL pass.\n"); From 809b94a67b0b666018b35536d4de327e99378a6f Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Mon, 8 Jul 2019 12:24:24 -0700 Subject: [PATCH 2/7] intel_synth: Make family explicit and match The help and code default to MAX10 for the family, however the couple of if ladders defaulted to cycloneive. Fix this inconsistency and the next patch will clean it up. Signed-off-by: Ben Widawsky --- techlibs/intel/synth_intel.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 69f3b6334..9d5d593a4 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -176,8 +176,10 @@ struct SynthIntelPass : public ScriptPass { run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v"); else if (check_label("family") && family_opt == "cycloneiv") run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v"); - else + else if (check_label("family") && family_opt == "cycloneive") run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v"); + else + log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str()); // Misc and common cells run("read_verilog -sv -lib +/intel/common/m9k_bb.v"); run("read_verilog -sv -lib +/intel/common/altpll_bb.v"); @@ -236,8 +238,10 @@ struct SynthIntelPass : public ScriptPass { run("techmap -map +/intel/cyclone10/cells_map.v"); else if (family_opt == "cycloneiv") run("techmap -map +/intel/cycloneiv/cells_map.v"); - else + else if (family_opt == "cycloneive") run("techmap -map +/intel/cycloneive/cells_map.v"); + else + log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str()); run("dffinit -highlow -ff dffeas q power_up"); run("clean -purge"); } From f950a7a75d4353e0e31c523365a10926bc6180af Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Mon, 8 Jul 2019 12:37:24 -0700 Subject: [PATCH 3/7] intel_synth: Small code cleanup to remove if ladder Signed-off-by: Ben Widawsky --- examples/intel/MAX10/run_max10 | 2 +- techlibs/intel/synth_intel.cc | 38 +++++++++------------------------- 2 files changed, 11 insertions(+), 29 deletions(-) diff --git a/examples/intel/MAX10/run_max10 b/examples/intel/MAX10/run_max10 index 0378e4fa7..5bf4fc141 100644 --- a/examples/intel/MAX10/run_max10 +++ b/examples/intel/MAX10/run_max10 @@ -1 +1 @@ -yosys -p "synth_intel -family max10 -top top -vqm top.vqm" top.v sevenseg.v +../../../yosys -p "synth_intel -family max10 -top top -vqm top.vqm" top.v sevenseg.v diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 9d5d593a4..5d6254ff6 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -166,20 +166,12 @@ struct SynthIntelPass : public ScriptPass { void script() YS_OVERRIDE { if (check_label("begin")) { - if (check_label("family") && family_opt == "max10") - run("read_verilog -sv -lib +/intel/max10/cells_sim.v"); - else if (check_label("family") && family_opt == "a10gx") - run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v"); - else if (check_label("family") && family_opt == "cyclonev") - run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v"); - else if (check_label("family") && family_opt == "cyclone10") - run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v"); - else if (check_label("family") && family_opt == "cycloneiv") - run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v"); - else if (check_label("family") && family_opt == "cycloneive") - run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v"); - else - log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str()); + string cmd = "read_verilog -sv -lib +/intel/FAMILY/cells_sim.v"; + cmd.replace(cmd.find("FAMILY"), 6, family_opt); + + if (check_label("family")) + run(cmd); + // Misc and common cells run("read_verilog -sv -lib +/intel/common/m9k_bb.v"); run("read_verilog -sv -lib +/intel/common/altpll_bb.v"); @@ -228,20 +220,10 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_cells")) { if (!noiopads) run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)"); - if (family_opt == "max10") - run("techmap -map +/intel/max10/cells_map.v"); - else if (family_opt == "a10gx") - run("techmap -map +/intel/a10gx/cells_map.v"); - else if (family_opt == "cyclonev") - run("techmap -map +/intel/cyclonev/cells_map.v"); - else if (family_opt == "cyclone10") - run("techmap -map +/intel/cyclone10/cells_map.v"); - else if (family_opt == "cycloneiv") - run("techmap -map +/intel/cycloneiv/cells_map.v"); - else if (family_opt == "cycloneive") - run("techmap -map +/intel/cycloneive/cells_map.v"); - else - log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str()); + string cmd = "techmap -map +/intel/FAMILY/cells_map.v"; + cmd.replace(cmd.find("FAMILY"), 6, family_opt); + run(cmd); + run("dffinit -highlow -ff dffeas q power_up"); run("clean -purge"); } From 999811572a652a60003b98b120a5e2da20aad059 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Mon, 8 Jul 2019 12:41:22 -0700 Subject: [PATCH 4/7] intel_synth: Fix help message cyclonev has been a "supported" family since the initial commit. The old commit message suggested to use a10gx which is incorrect. Aside from the obvious lack of functional change due to this just being a help message, users who were previously using "a10gx" for "cyclonev" will also have no functional change by using "cyclonev" instead. Signed-off-by: Ben Widawsky --- techlibs/intel/synth_intel.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 5d6254ff6..0b44a835f 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -40,7 +40,7 @@ struct SynthIntelPass : public ScriptPass { log(" generate the synthesis netlist for the specified family.\n"); log(" MAX10 is the default target if not family argument specified.\n"); log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n"); - log(" Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n"); + log(" Cyclone V and Arria 10 GX devices are experimental.\n"); log("\n"); log(" -top \n"); log(" use the specified module as top module (default='top')\n"); From d5b3b3bc6f9461fcdbad3dce849b4ab8988515db Mon Sep 17 00:00:00 2001 From: Dan Ravensloft Date: Thu, 18 Jul 2019 17:08:52 +0100 Subject: [PATCH 5/7] synth_intel: revert change to run_max10 --- examples/intel/MAX10/run_max10 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/intel/MAX10/run_max10 b/examples/intel/MAX10/run_max10 index 5bf4fc141..0378e4fa7 100644 --- a/examples/intel/MAX10/run_max10 +++ b/examples/intel/MAX10/run_max10 @@ -1 +1 @@ -../../../yosys -p "synth_intel -family max10 -top top -vqm top.vqm" top.v sevenseg.v +yosys -p "synth_intel -family max10 -top top -vqm top.vqm" top.v sevenseg.v From 50f5e29724bb6ea7f19279be7613ce693b7ea2da Mon Sep 17 00:00:00 2001 From: Dan Ravensloft Date: Thu, 18 Jul 2019 17:28:21 +0100 Subject: [PATCH 6/7] synth_intel: s/not family/no family/ --- techlibs/intel/synth_intel.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 0b44a835f..9a6df8c45 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -38,7 +38,7 @@ struct SynthIntelPass : public ScriptPass { log("\n"); log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n"); log(" generate the synthesis netlist for the specified family.\n"); - log(" MAX10 is the default target if not family argument specified.\n"); + log(" MAX10 is the default target if no family argument specified.\n"); log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n"); log(" Cyclone V and Arria 10 GX devices are experimental.\n"); log("\n"); @@ -153,7 +153,7 @@ struct SynthIntelPass : public ScriptPass { family_opt != "cycloneiv" && family_opt != "cycloneive" && family_opt != "cyclone10") - log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str()); + log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str()); log_header(design, "Executing SYNTH_INTEL pass.\n"); log_push(); From 0c999ac2c4379273d560319d28591627de345a6a Mon Sep 17 00:00:00 2001 From: Dan Ravensloft Date: Thu, 18 Jul 2019 18:41:34 +0100 Subject: [PATCH 7/7] synth_intel: Use stringf --- techlibs/intel/synth_intel.cc | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 9a6df8c45..58ef25e17 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -166,11 +166,8 @@ struct SynthIntelPass : public ScriptPass { void script() YS_OVERRIDE { if (check_label("begin")) { - string cmd = "read_verilog -sv -lib +/intel/FAMILY/cells_sim.v"; - cmd.replace(cmd.find("FAMILY"), 6, family_opt); - if (check_label("family")) - run(cmd); + run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str())); // Misc and common cells run("read_verilog -sv -lib +/intel/common/m9k_bb.v"); @@ -220,9 +217,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_cells")) { if (!noiopads) run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)"); - string cmd = "techmap -map +/intel/FAMILY/cells_map.v"; - cmd.replace(cmd.find("FAMILY"), 6, family_opt); - run(cmd); + run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str())); run("dffinit -highlow -ff dffeas q power_up"); run("clean -purge");