riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

synth_intel: Use stringf

This commit is contained in:
Dan Ravensloft 2019-07-18 18:41:34 +01:00
parent 50f5e29724
commit 0c999ac2c4
1 changed files with 2 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
techlibs/intel/synth_intel.cc
View File

@ -166,11 +166,8 @@ struct SynthIntelPass : public ScriptPass {
void script() YS_OVERRIDE
{
if (check_label("begin")) {
string cmd = "read_verilog -sv -lib +/intel/FAMILY/cells_sim.v";
cmd.replace(cmd.find("FAMILY"), 6, family_opt);
if (check_label("family"))
run(cmd);
run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
// Misc and common cells
run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
@ -220,9 +217,7 @@ struct SynthIntelPass : public ScriptPass {
if (check_label("map_cells")) {
if (!noiopads)
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
string cmd = "techmap -map +/intel/FAMILY/cells_map.v";
cmd.replace(cmd.find("FAMILY"), 6, family_opt);
run(cmd);
run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
run("dffinit -highlow -ff dffeas q power_up");
run("clean -purge");