mirror of https://github.com/YosysHQ/yosys.git
Fixed "flatten" for non-pre-derived modules
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@ -1088,7 +1088,7 @@ struct FlattenPass : public Pass {
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if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, false))
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did_something = true;
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} else {
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for (auto mod : design->modules())
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for (auto mod : vector<Module*>(design->modules()))
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if (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false))
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did_something = true;
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}
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@ -1098,7 +1098,7 @@ struct FlattenPass : public Pass {
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if (top_mod != NULL) {
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dict<RTLIL::IdString, RTLIL::Module*> new_modules;
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for (auto mod : design->modules())
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for (auto mod : vector<Module*>(design->modules()))
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if (mod == top_mod || mod->get_bool_attribute("\\blackbox")) {
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new_modules[mod->name] = mod;
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} else {
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