mirror of https://github.com/YosysHQ/yosys.git
Added "equiv_struct -maxiter <N>"
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@ -114,11 +114,11 @@ struct EquivStructWorker
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module->remove(cell_b);
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}
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EquivStructWorker(Module *module, bool mode_fwd, bool mode_icells) :
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EquivStructWorker(Module *module, bool mode_fwd, bool mode_icells, int iter_num) :
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module(module), sigmap(module), equiv_bits(module),
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mode_fwd(mode_fwd), mode_icells(mode_icells), merge_count(0)
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{
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log(" Starting new iteration.\n");
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log(" Starting iteration %d.\n", iter_num);
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pool<SigBit> equiv_inputs;
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pool<IdString> cells;
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@ -296,11 +296,15 @@ struct EquivStructPass : public Pass {
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log(" by default, the internal RTL and gate cell types are ignored. add\n");
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log(" this option to also process those cell types with this command.\n");
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log("\n");
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log(" -maxiter <N>\n");
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log(" maximum number of iterations to run before aborting\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, Design *design)
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{
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bool mode_icells = false;
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bool mode_fwd = false;
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int max_iter = -1;
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log_header("Executing EQUIV_STRUCT pass.\n");
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@ -314,6 +318,10 @@ struct EquivStructPass : public Pass {
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mode_icells = true;
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continue;
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}
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if (args[argidx] == "-maxiter" && argidx+1 < args.size()) {
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max_iter = atoi(args[++argidx].c_str());
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -321,8 +329,12 @@ struct EquivStructPass : public Pass {
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for (auto module : design->selected_modules()) {
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int module_merge_count = 0;
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log("Running equiv_struct on module %s:\n", log_id(module));
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while (1) {
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EquivStructWorker worker(module, mode_fwd, mode_icells);
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for (int iter = 0;; iter++) {
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if (iter == max_iter) {
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log(" Reached iteration limit of %d.\n", iter);
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break;
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}
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EquivStructWorker worker(module, mode_fwd, mode_icells, iter+1);
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if (worker.merge_count == 0)
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break;
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module_merge_count += worker.merge_count;
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