mirror of https://github.com/YosysHQ/yosys.git
Added expose command
This commit is contained in:
Clifford Wolf
parent
7e9ba60df8
commit
cd06055e77
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@ -3,4 +3,5 @@ OBJS += passes/sat/sat.o
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OBJS += passes/sat/freduce.o
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OBJS += passes/sat/eval.o
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OBJS += passes/sat/miter.o
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OBJS += passes/sat/expose.o
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@ -0,0 +1,263 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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static bool consider_wire(RTLIL::Wire *wire)
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{
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if (wire->name[0] == '$')
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return false;
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if (wire->port_input)
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return false;
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return true;
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}
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static bool consider_cell(RTLIL::Design *design, RTLIL::Cell *cell)
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{
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if (cell->name[0] == '$')
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return false;
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if (design->modules.count(cell->type) == 0)
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return false;
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return true;
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}
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static bool compare_wires(RTLIL::Wire *wire1, RTLIL::Wire *wire2)
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{
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log_assert(wire1->name == wire2->name);
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if (wire1->width != wire2->width)
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return false;
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return true;
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}
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static bool compare_cells(RTLIL::Cell *cell1, RTLIL::Cell *cell2)
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{
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log_assert(cell1->name == cell2->name);
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if (cell1->type != cell2->type)
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return false;
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if (cell1->parameters != cell2->parameters)
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return false;
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return true;
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}
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struct ExposePass : public Pass {
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ExposePass() : Pass("expose", "convert internal signals to module ports") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" expose [options] [selection]\n");
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log("\n");
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log("This command exposes all selected internal signals of a module as additional\n");
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log("outputs.\n");
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log("\n");
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log(" -shared\n");
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log(" only expose those signals that are shared ammong the selected modules.\n");
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log(" this is useful for preparing modules for equivialence checking.\n");
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log("\n");
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log(" -evert\n");
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log(" also turn connections to instances of other modules to additional\n");
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log(" inputs and outputs and remove the module instances.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_shared = false;
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bool flag_evert = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-shared") {
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flag_shared = true;
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continue;
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}
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if (args[argidx] == "-evert") {
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flag_evert = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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std::set<std::string> shared_wires, shared_cells;
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std::set<std::string> used_names;
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if (flag_shared)
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{
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RTLIL::Module *first_module = NULL;
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for (auto &mod_it : design->modules)
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{
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RTLIL::Module *module = mod_it.second;
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if (!design->selected(module))
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continue;
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if (first_module == NULL)
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{
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for (auto &it : module->wires)
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if (design->selected(module, it.second) && consider_wire(it.second))
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shared_wires.insert(it.first);
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if (flag_evert)
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for (auto &it : module->cells)
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if (design->selected(module, it.second) && consider_cell(design, it.second))
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shared_cells.insert(it.first);
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first_module = module;
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}
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else
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{
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std::vector<std::string> delete_shared_wires, delete_shared_cells;
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for (auto &it : shared_wires)
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{
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RTLIL::Wire *wire;
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if (module->wires.count(it) == 0)
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goto delete_shared_wire;
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wire = module->wires.at(it);
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if (!design->selected(module, wire))
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goto delete_shared_wire;
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if (!consider_wire(wire))
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goto delete_shared_wire;
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if (!compare_wires(first_module->wires.at(it), wire))
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goto delete_shared_wire;
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if (0)
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delete_shared_wire:
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delete_shared_wires.push_back(it);
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}
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if (flag_evert)
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for (auto &it : shared_cells)
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{
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RTLIL::Cell *cell;
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if (module->cells.count(it) == 0)
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goto delete_shared_cell;
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cell = module->cells.at(it);
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if (!design->selected(module, cell))
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goto delete_shared_cell;
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if (!consider_cell(design, cell))
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goto delete_shared_cell;
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if (!compare_cells(first_module->cells.at(it), cell))
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goto delete_shared_cell;
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if (0)
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delete_shared_cell:
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delete_shared_cells.push_back(it);
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}
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for (auto &it : delete_shared_wires)
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shared_wires.erase(it);
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for (auto &it : delete_shared_cells)
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shared_cells.erase(it);
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}
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}
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}
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for (auto &mod_it : design->modules)
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{
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RTLIL::Module *module = mod_it.second;
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if (!design->selected(module))
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continue;
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for (auto &it : module->wires)
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{
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if (flag_shared) {
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if (shared_wires.count(it.first) == 0)
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continue;
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} else {
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if (!design->selected(module, it.second) || !consider_wire(it.second))
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continue;
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}
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if (!it.second->port_output) {
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it.second->port_output = true;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name));
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}
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}
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if (flag_evert)
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{
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std::vector<std::string> delete_cells;
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for (auto &it : module->cells)
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{
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if (flag_shared) {
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if (shared_cells.count(it.first) == 0)
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continue;
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} else {
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if (!design->selected(module, it.second) || !consider_cell(design, it.second))
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continue;
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}
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RTLIL::Cell *cell = it.second;
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RTLIL::Module *mod = design->modules.at(cell->type);
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for (auto &it : mod->wires)
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{
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RTLIL::Wire *p = it.second;
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if (!p->port_input && !p->port_output)
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continue;
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RTLIL::Wire *w = new RTLIL::Wire;
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w->name = cell->name + "." + RTLIL::unescape_id(p->name);
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w->width = p->width;
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if (p->port_input)
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w->port_output = true;
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if (p->port_output)
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w->port_input = true;
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module->add(w);
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
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RTLIL::SigSpec sig;
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if (cell->connections.count(p->name) != 0)
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sig = cell->connections.at(p->name);
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sig.extend(w->width);
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if (w->port_input)
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module->connections.push_back(RTLIL::SigSig(sig, w));
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else
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module->connections.push_back(RTLIL::SigSig(w, sig));
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}
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delete_cells.push_back(cell->name);
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}
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for (auto &it : delete_cells) {
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log("Removing cell: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it));
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delete module->cells.at(it);
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module->cells.erase(it);
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}
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}
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module->fixup_ports();
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}
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}
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} ExposePass;
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