mirror of https://github.com/YosysHQ/yosys.git
Improved opt_share for commutative standard cells
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@ -65,7 +65,20 @@ struct OptShareWorker
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for (auto &it : cell->parameters)
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hash_string += "P " + it.first + "=" + it.second.as_string() + "\n";
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for (auto &it : cell->connections) {
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const std::map<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections;
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std::map<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
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if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" ||
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cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") {
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alt_conn = *conn;
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if (assign_map(alt_conn.at("\\A")) < assign_map(alt_conn.at("\\B"))) {
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alt_conn["\\A"] = conn->at("\\B");
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alt_conn["\\B"] = conn->at("\\A");
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}
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conn = &alt_conn;
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}
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for (auto &it : *conn) {
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if (ct.cell_output(cell->type, it.first))
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continue;
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RTLIL::SigSpec sig = it.second;
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@ -126,6 +139,20 @@ struct OptShareWorker
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assign_map.apply(it.second);
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}
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if (cell1->type == "$and" || cell1->type == "$or" || cell1->type == "$xor" || cell1->type == "$xnor" || cell1->type == "$add" || cell1->type == "$mul" ||
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cell1->type == "$logic_and" || cell1->type == "$logic_or" || cell1->type == "$_AND_" || cell1->type == "$_OR_" || cell1->type == "$_XOR_") {
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if (conn1.at("\\A") < conn1.at("\\B")) {
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RTLIL::SigSpec tmp = conn1["\\A"];
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conn1["\\A"] = conn1["\\B"];
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conn1["\\B"] = tmp;
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}
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if (conn2.at("\\A") < conn2.at("\\B")) {
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RTLIL::SigSpec tmp = conn2["\\A"];
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conn2["\\A"] = conn2["\\B"];
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conn2["\\B"] = tmp;
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}
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}
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if (conn1 != conn2) {
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lt = conn1 < conn2;
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return true;
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