mirror of https://github.com/YosysHQ/yosys.git
Various improvements in sat_solve pass and SAT generator
This commit is contained in:
Clifford Wolf
parent
99957a825f
commit
1434312fdd
112
kernel/satgen.h
112
kernel/satgen.h
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@ -73,29 +73,6 @@ struct SatGen
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return vec;
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}
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// ** cell types to be done: **
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// cell_types.insert("$pos");
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// cell_types.insert("$neg");
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// cell_types.insert("$xnor");
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// cell_types.insert("$reduce_and");
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// cell_types.insert("$reduce_or");
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// cell_types.insert("$reduce_xor");
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// cell_types.insert("$reduce_xnor");
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// cell_types.insert("$reduce_bool");
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// cell_types.insert("$shl");
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// cell_types.insert("$shr");
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// cell_types.insert("$sshl");
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// cell_types.insert("$sshr");
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// cell_types.insert("$mul");
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// cell_types.insert("$div");
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// cell_types.insert("$mod");
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// cell_types.insert("$pow");
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// cell_types.insert("$logic_not");
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// cell_types.insert("$logic_and");
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// cell_types.insert("$logic_or");
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// cell_types.insert("$pmux");
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// cell_types.insert("$safe_pmux");
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void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell)
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{
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bool is_signed_a = false, is_signed_b = false;
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@ -116,10 +93,10 @@ struct SatGen
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vec_y.push_back(ez->literal());
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}
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virtual void importCell(RTLIL::Cell *cell)
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virtual bool importCell(RTLIL::Cell *cell)
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{
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if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_" ||
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cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" ||
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cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" ||
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cell->type == "$add" || cell->type == "$sub") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
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std::vector<int> b = importSigSpec(cell->connections.at("\\B"));
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@ -131,23 +108,91 @@ struct SatGen
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ez->assume(ez->vec_eq(ez->vec_or(a, b), y));
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if (cell->type == "$xor" || cell->type == "$_XOR")
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ez->assume(ez->vec_eq(ez->vec_xor(a, b), y));
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if (cell->type == "$xnor")
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ez->assume(ez->vec_eq(ez->vec_not(ez->vec_xor(a, b)), y));
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if (cell->type == "$add")
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ez->assume(ez->vec_eq(ez->vec_add(a, b), y));
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if (cell->type == "$sub")
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ez->assume(ez->vec_eq(ez->vec_sub(a, b), y));
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} else
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return true;
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}
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if (cell->type == "$_INV_" || cell->type == "$not") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
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ez->assume(ez->vec_eq(ez->vec_not(a), y));
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} else
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return true;
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}
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if (cell->type == "$_MUX_" || cell->type == "$mux") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
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std::vector<int> b = importSigSpec(cell->connections.at("\\B"));
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std::vector<int> s = importSigSpec(cell->connections.at("\\S"));
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
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ez->assume(ez->vec_eq(ez->vec_ite(s, b, a), y));
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} else
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ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), y));
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return true;
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}
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if (cell->type == "$pmux" || cell->type == "$safe_pmux") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
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std::vector<int> b = importSigSpec(cell->connections.at("\\B"));
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std::vector<int> s = importSigSpec(cell->connections.at("\\S"));
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
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std::vector<int> tmp = a;
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for (size_t i = 0; i < s.size(); i++) {
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std::vector<int> part_of_b(b.begin()+i*a.size(), b.begin()+(i+1)*a.size());
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tmp = ez->vec_ite(s.at(i), part_of_b, tmp);
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}
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if (cell->type == "$safe_pmux")
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tmp = ez->vec_ite(ez->onehot(s, true), tmp, a);
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ez->assume(ez->vec_eq(tmp, y));
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return true;
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}
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if (cell->type == "$pos" || cell->type == "$neg") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
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if (cell->type == "$pos") {
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ez->assume(ez->vec_eq(a, y));
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} else {
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std::vector<int> zero(a.size(), ez->FALSE);
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ez->assume(ez->vec_eq(ez->vec_sub(zero, a), y));
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}
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return true;
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}
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if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
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cell->type == "$reduce_xnor" || cell->type == "$reduce_bool" || cell->type == "$logic_not") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
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if (cell->type == "$reduce_and")
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ez->SET(ez->expression(ez->OpAnd, a), y.at(0));
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if (cell->type == "$reduce_or" || cell->type == "$reduce_bool")
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ez->SET(ez->expression(ez->OpOr, a), y.at(0));
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if (cell->type == "$reduce_xor")
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ez->SET(ez->expression(ez->OpXor, a), y.at(0));
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if (cell->type == "$reduce_xnor")
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ez->SET(ez->NOT(ez->expression(ez->OpXor, a)), y.at(0));
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if (cell->type == "$logic_not")
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ez->SET(ez->NOT(ez->expression(ez->OpOr, a)), y.at(0));
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for (size_t i = 1; i < y.size(); i++)
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ez->SET(0, y.at(0));
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return true;
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}
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if (cell->type == "$logic_and" || cell->type == "$logic_or") {
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int a = ez->expression(ez->OpOr, importSigSpec(cell->connections.at("\\A")));
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int b = ez->expression(ez->OpOr, importSigSpec(cell->connections.at("\\B")));
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"));
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if (cell->type == "$logic_and")
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ez->SET(ez->expression(ez->OpAnd, a, b), y.at(0));
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else
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ez->SET(ez->expression(ez->OpOr, a, b), y.at(0));
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for (size_t i = 1; i < y.size(); i++)
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ez->SET(0, y.at(0));
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return true;
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}
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if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || cell->type == "$ge" || cell->type == "$gt") {
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bool is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool();
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"));
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@ -166,8 +211,13 @@ struct SatGen
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ez->SET(is_signed ? ez->vec_ge_signed(a, b) : ez->vec_ge_unsigned(a, b), y.at(0));
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if (cell->type == "$gt")
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ez->SET(is_signed ? ez->vec_gt_signed(a, b) : ez->vec_gt_unsigned(a, b), y.at(0));
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} else
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log_error("Can't handle cell type %s in SAT generator yet.\n", RTLIL::id2cstr(cell->type));
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for (size_t i = 1; i < y.size(); i++)
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ez->SET(0, y.at(0));
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return true;
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}
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// Unsupported internal cell types: $shl $shr $sshl $sshr $mul $div $mod $pow
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return false;
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}
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};
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@ -1,5 +1,5 @@
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module example(a, y);
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module example001(a, y);
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input [15:0] a;
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output y;
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@ -10,3 +10,63 @@ assign y = !gt && !lt;
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endmodule
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// ------------------------------------
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module example002(a, y);
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input [3:0] a;
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output y;
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reg [1:0] t1, t2;
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always @* begin
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casex (a)
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16'b1xxx:
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t1 <= 1;
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16'bx1xx:
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t1 <= 2;
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16'bxx1x:
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t1 <= 3;
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16'bxxx1:
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t1 <= 4;
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default:
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t1 <= 0;
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endcase
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casex (a)
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16'b1xxx:
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t2 <= 1;
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16'b01xx:
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t2 <= 2;
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16'b001x:
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t2 <= 3;
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16'b0001:
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t2 <= 4;
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default:
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t2 <= 0;
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endcase
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end
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assign y = t1 != t2;
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endmodule
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// ------------------------------------
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module example003(clk, rst, y);
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input clk, rst;
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output y;
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reg [3:0] counter;
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always @(posedge clk)
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case (1)
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rst, counter == 9:
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counter <= 0;
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default:
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counter <= counter+1;
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endcase
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assign y = counter == 12;
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endmodule
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@ -1,3 +1,5 @@
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read_verilog example.v
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techmap; opt; abc; opt
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sat_solve -set y 1'b1
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proc; opt_clean
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sat_solve -set y 1'b1 example001
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sat_solve -set y 1'b1 example002
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sat_solve -set y 1'b1 example003
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@ -211,14 +211,16 @@ struct SatSolvePass : public Pass {
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int import_cell_counter = 0;
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for (auto &c : module->cells)
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if (design->selected(module, c.second) && ct.cell_known(c.second->type)) {
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for (auto &p : c.second->connections)
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if (ct.cell_output(c.second->type, p.first))
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show_drivers.insert(sigmap(p.second), c.second);
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else
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show_driven[c.second].append(sigmap(p.second));
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// log("Import cell: %s\n", RTLIL::id2cstr(c.first));
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satgen.importCell(c.second);
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import_cell_counter++;
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if (satgen.importCell(c.second)) {
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for (auto &p : c.second->connections)
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if (ct.cell_output(c.second->type, p.first))
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show_drivers.insert(sigmap(p.second), c.second);
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else
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show_driven[c.second].append(sigmap(p.second));
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import_cell_counter++;
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} else
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log("Warning: failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
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}
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log("Imported %d cells to SAT database.\n", import_cell_counter);
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