mirror of https://github.com/YosysHQ/yosys.git
Added "rename -top new_name"
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@ -316,6 +316,21 @@ RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
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return modules_.count(name) ? modules_.at(name) : NULL;
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}
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RTLIL::Module *RTLIL::Design::top_module()
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{
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RTLIL::Module *module = nullptr;
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int module_count = 0;
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for (auto mod : selected_modules()) {
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if (mod->get_bool_attribute("\\top"))
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return mod;
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module_count++;
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module = mod;
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}
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return module_count == 1 ? module : nullptr;
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}
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void RTLIL::Design::add(RTLIL::Module *module)
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{
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log_assert(modules_.count(module->name) == 0);
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@ -800,6 +800,7 @@ struct RTLIL::Design
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RTLIL::ObjRange<RTLIL::Module*> modules();
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RTLIL::Module *module(RTLIL::IdString name);
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RTLIL::Module *top_module();
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bool has(RTLIL::IdString id) const {
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return modules_.count(id) != 0;
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@ -76,12 +76,17 @@ struct RenamePass : public Pass {
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log("Assign private names (the ones with $-prefix) to all selected wires and cells\n");
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log("with public names. This ignores all selected ports.\n");
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log("\n");
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log(" rename -top new_name\n");
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log("\n");
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log("Rename top module.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::string pattern_prefix = "_", pattern_suffix = "_";
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bool flag_enumerate = false;
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bool flag_hide = false;
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bool flag_top = false;
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bool got_mode = false;
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size_t argidx;
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@ -98,6 +103,11 @@ struct RenamePass : public Pass {
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got_mode = true;
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continue;
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}
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if (arg == "-top" && !got_mode) {
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flag_top = true;
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got_mode = true;
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continue;
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}
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if (arg == "-pattern" && argidx+1 < args.size() && args[argidx+1].find('%') != std::string::npos) {
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int pos = args[++argidx].find('%');
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pattern_prefix = args[argidx].substr(0, pos);
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@ -171,6 +181,23 @@ struct RenamePass : public Pass {
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}
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}
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else
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if (flag_top)
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{
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if (argidx+1 != args.size())
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log_cmd_error("Invalid number of arguments!\n");
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IdString new_name = RTLIL::escape_id(args[argidx]);
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RTLIL::Module *module = design->top_module();
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if (module == NULL)
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log_cmd_error("No top module found!\n");
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log("Renaming module %s to %s.\n", log_id(module), log_id(new_name));
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design->modules_.erase(module->name);
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module->name = new_name;
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design->modules_[module->name] = module;
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}
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else
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{
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if (argidx+2 != args.size())
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log_cmd_error("Invalid number of arguments!\n");
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