mirror of https://github.com/YosysHQ/yosys.git
opt_lut: use a worklist, and revisit cells affected by elimination.
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f7363ac508
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@ -189,7 +189,8 @@ struct OptLutWorker
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log("\n");
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log("Eliminating LUTs.\n");
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for (auto lut : luts)
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pool<RTLIL::Cell*> worklist = luts;
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while (worklist.size())
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{
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if (limit == 0)
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{
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@ -197,6 +198,7 @@ struct OptLutWorker
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break;
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}
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auto lut = worklist.pop();
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SigSpec lut_input = sigmap(lut->getPort("\\A"));
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pool<int> &lut_dlogic_inputs = luts_dlogic_inputs[lut];
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@ -262,8 +264,13 @@ struct OptLutWorker
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else
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{
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SigSpec lut_output = lut->getPort("\\Y");
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module->connect(lut_output, value);
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for (auto &port : index.query_ports(lut_output))
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{
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if (port.cell != lut && luts.count(port.cell))
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worklist.insert(port.cell);
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}
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module->connect(lut_output, value);
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module->remove(lut);
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luts.erase(lut);
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luts_arity.erase(lut);
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@ -280,7 +287,7 @@ struct OptLutWorker
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log("\n");
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log("Combining LUTs.\n");
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pool<RTLIL::Cell*> worklist = luts;
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worklist = luts;
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while (worklist.size())
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{
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if (limit == 0)
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