mirror of https://github.com/YosysHQ/yosys.git
Disable memory_dff for initialized FFs
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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commit
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@ -33,8 +33,20 @@ struct MemoryDffWorker
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dict<SigBit, int> sigbit_users_count;
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dict<SigSpec, Cell*> mux_cells_a, mux_cells_b;
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pool<Cell*> forward_merged_dffs, candidate_dffs;
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pool<SigBit> init_bits;
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MemoryDffWorker(Module *module) : module(module), sigmap(module) { }
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MemoryDffWorker(Module *module) : module(module), sigmap(module)
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{
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for (auto wire : module->wires()) {
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if (wire->attributes.count("\\init") == 0)
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continue;
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SigSpec sig = sigmap(wire);
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Const initval = wire->attributes.count("\\init");
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for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
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if (initval[i] == State::S0 || initval[i] == State::S1)
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init_bits.insert(sig[i]);
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}
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}
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bool find_sig_before_dff(RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
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{
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@ -45,6 +57,9 @@ struct MemoryDffWorker
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if (bit.wire == NULL)
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continue;
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if (!after && init_bits.count(sigmap(bit)))
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return false;
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for (auto cell : dff_cells)
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{
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if (after && forward_merged_dffs.count(cell))
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@ -72,6 +87,9 @@ struct MemoryDffWorker
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if (d.size() != 1)
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continue;
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if (after && init_bits.count(d))
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return false;
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bit = d;
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clk = this_clk;
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clk_polarity = this_clk_polarity;
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