riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed bug in memory_share for memory ports with different ABITS

This commit is contained in:
Clifford Wolf 2016-08-22 14:26:33 +02:00
parent 7a33b9892a
commit cad40fc874
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
passes/memory/memory_share.cc
View File

@ -619,6 +619,12 @@ struct MemoryShareWorker
RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
if (GetSize(last_addr) < GetSize(this_addr))
last_addr.extend_u0(GetSize(this_addr));
else
this_addr.extend_u0(GetSize(last_addr));
wr_ports[i]->setParam("\\ABITS", GetSize(this_addr));
wr_ports[i]->setPort("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
wr_ports[i]->setPort("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active));