mirror of https://github.com/YosysHQ/yosys.git
Reduced log verbosity
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ad19e0c64a
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1b42e0c471
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@ -202,13 +202,12 @@ void counters_worker(ModIndex& index, Module */*module*/, Cell *cell, unsigned i
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//Log it
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total_counters ++;
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log(" Extracting %d-bit counter to %s hard macro\n", a_width, celltype.c_str());
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log(" Decrementer: %s\n", cell->name.c_str());
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log(" Output mux: %s\n", count_mux->name.c_str());
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log(" Register: %s\n", count_reg->name.c_str());
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log(" Comparator: %s\n", underflow_inv->name.c_str());
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log(" Count value: %d\n", count_value);
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string count_reg_src = rwire->attributes["\\src"].decode_string().c_str();
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log(" Found %d-bit non-resettable down counter (from %d) for register %s declared at %s\n",
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a_width,
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count_value,
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log_id(rwire->name),
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count_reg_src.c_str());
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/*
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log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell));
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@ -240,12 +239,12 @@ struct CountersPass : public Pass {
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log("\n");
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log(" counters [options] [selection]\n");
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log("\n");
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log("This pass converts resettable down counters to GreenPak counter cells\n");
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log("This pass converts resettable down counters to GreenPak4 counter cells\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing COUNTERS pass (mapping counters to GP_COUNTx cells).\n");
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log_header("Executing COUNTERS pass (mapping counters to hard IP blocks).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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