mirror of https://github.com/YosysHQ/yosys.git
Add support {A,B,P}REG packing
This commit is contained in:
Eddie Hung
parent
d086dfb5b0
commit
9616dbd125
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@ -25,46 +25,60 @@ PRIVATE_NAMESPACE_BEGIN
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#include "passes/pmgen/xilinx_dsp_pm.h"
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void create_xilinx_dsp(xilinx_dsp_pm &pm)
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void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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{
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auto &st = pm.st_xilinx_dsp;
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#if 0
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#if 1
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log("\n");
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log("ffA: %s\n", log_id(st.ffA, "--"));
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log("ffB: %s\n", log_id(st.ffB, "--"));
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log("mul: %s\n", log_id(st.mul, "--"));
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log("ffY: %s\n", log_id(st.ffY, "--"));
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log("dsp: %s\n", log_id(st.dsp, "--"));
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log("ffP: %s\n", log_id(st.ffP, "--"));
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log("muxP: %s\n", log_id(st.muxP, "--"));
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log("P_WIDTH: %d\n", st.P_WIDTH);
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#endif
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log("Analysing %s.%s for Xilinx DSP register packing.\n", log_id(pm.module), log_id(st.mul));
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log("Analysing %s.%s for Xilinx DSP register packing.\n", log_id(pm.module), log_id(st.dsp));
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Cell *cell = st.mul;
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Cell *cell = st.dsp;
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log_assert(cell);
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// Input Interface
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cell->setPort("\\A", st.sigA);
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cell->setPort("\\B", st.sigB);
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cell->setParam("\\AREG", st.ffA ? State::S1 : State::S0);
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cell->setParam("\\BREG", st.ffB ? State::S1 : State::S0);
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if (st.clock != SigBit())
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{
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cell->setPort("\\CLK", st.clock);
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if (st.ffA) {
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SigSpec D = st.ffA->getPort("\\D");
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cell->setPort("\\A", D.extend_u0(30));
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cell->setParam("\\AREG", State::S1);
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cell->setPort("\\CEA2", State::S1);
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if (st.ffA->type == "$dff")
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cell->setPort("\\CEA2", State::S1);
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else if (st.ffA->type == "$dffe")
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cell->setPort("\\CEA2", st.ffA->getPort("\\EN"));
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else log_abort();
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}
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if (st.ffB) {
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SigSpec D = st.ffB->getPort("\\D");
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cell->setPort("\\B", D.extend_u0(18));
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cell->setParam("\\BREG", State::S1);
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cell->setPort("\\CEA2", State::S1);
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if (st.ffB->type == "$dff")
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cell->setPort("\\CEB2", State::S1);
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else if (st.ffB->type == "$dffe")
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cell->setPort("\\CEB2", st.ffB->getPort("\\EN"));
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else log_abort();
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}
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if (st.ffY) {
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cell->setPort("\\PREG", State::S1);
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cell->setPort("\\CEP", State::S1);
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if (st.ffP) {
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SigSpec P = cell->getPort("\\P");
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SigSpec Q = st.ffP->getPort("\\Q");
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Q.append(P.extract(GetSize(Q), -1));
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cell->setPort("\\P", Q);
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cell->setParam("\\PREG", State::S1);
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if (st.ffP->type == "$dff")
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cell->setPort("\\CEP", State::S1);
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else if (st.ffP->type == "$dffe")
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cell->setPort("\\CEP", st.ffP->getPort("\\EN"));
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else log_abort();
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}
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log(" clock: %s (%s)", log_signal(st.clock), "posedge");
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@ -75,15 +89,17 @@ void create_xilinx_dsp(xilinx_dsp_pm &pm)
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if (st.ffB)
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log(" ffB:%s", log_id(st.ffB));
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if (st.ffY)
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log(" ffY:%s", log_id(st.ffY));
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if (st.ffP)
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log(" ffY:%s", log_id(st.ffP));
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log("\n");
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}
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// Output Interface
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pm.autoremove(st.ffY);
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pm.autoremove(st.ffA);
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pm.autoremove(st.ffB);
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pm.autoremove(st.ffP);
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pm.autoremove(st.muxP);
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pm.blacklist(cell);
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}
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struct Ice40DspPass : public Pass {
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@ -99,7 +115,7 @@ struct Ice40DspPass : public Pass {
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ICE40_DSP pass (map multipliers).\n");
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log_header(design, "Executing XILINX_DSP pass (pack DSPs).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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@ -113,7 +129,7 @@ struct Ice40DspPass : public Pass {
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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xilinx_dsp_pm(module, module->selected_cells()).run_xilinx_dsp(create_xilinx_dsp);
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xilinx_dsp_pm(module, module->selected_cells()).run_xilinx_dsp(pack_xilinx_dsp);
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}
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} Ice40DspPass;
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@ -1,44 +1,36 @@
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pattern xilinx_dsp
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state <SigBit> clock
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state <SigSpec> sigA sigB sigY sigS
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state <Cell*> addAB muxAB
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state <int> P_WIDTH
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match mul
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select mul->type.in($__MUL25X18)
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match dsp
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select dsp->type.in(\DSP48E1)
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endmatch
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match ffA
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select ffA->type.in($dff) /* TODO: $dffe */
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select ffA->type.in($dff, $dffe)
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// select nusers(port(ffA, \Q)) == 2
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index <SigSpec> port(ffA, \Q) === port(mul, \A)
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index <SigSpec> port(ffA, \Q).extend_u0(30) === port(dsp, \A)
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// DSP48E1 does not support clock inversion
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index <SigBit> port(ffA, \CLK_POLARITY) === State::S1
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index <Const> param(ffA, \CLK_POLARITY).as_bool() === true
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optional
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endmatch
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code sigA clock
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sigA = port(mul, \A);
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if (ffA) {
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sigA = port(ffA, \D);
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code clock
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if (ffA)
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clock = port(ffA, \CLK).as_bit();
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}
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endcode
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match ffB
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select ffB->type.in($dff)
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select ffB->type.in($dff, $dffe)
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// select nusers(port(ffB, \Q)) == 2
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index <SigSpec> port(ffB, \Q) === port(mul, \B)
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index <SigBit> port(ffB, \CLK_POLARITY) === State::S1
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index <SigSpec> port(ffB, \Q).extend_u0(18) === port(dsp, \B)
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index <Const> param(ffB, \CLK_POLARITY).as_bool() === true
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optional
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endmatch
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code sigB clock
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sigB = port(mul, \B);
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code clock
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if (ffB) {
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sigB = port(ffB, \D);
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SigBit c = port(ffB, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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@ -48,20 +40,51 @@ code sigB clock
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}
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endcode
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match ffY
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select ffY->type.in($dff)
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select nusers(port(ffY, \D)) == 2
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index <SigSpec> port(ffY, \D) === port(mul, \Y)
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index <SigBit> port(ffY, \CLK_POLARITY) === State::S1
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code P_WIDTH
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SigSpec P = port(dsp, \P);
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int i;
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for (i = GetSize(P); i > 0; i--)
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if (nusers(P[i-1]) > 1)
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break;
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P_WIDTH = i;
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endcode
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match ffP
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select ffP->type.in($dff, $dffe)
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select nusers(port(ffP, \D)) == 2
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filter param(ffP, \WIDTH).as_int() == P_WIDTH
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filter port(ffP, \D) == port(dsp, \P).extract(0, P_WIDTH)
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index <Const> param(ffP, \CLK_POLARITY) === State::S1
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optional
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endmatch
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code sigY clock
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sigY = port(mul, \Y);
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// $mux cell left behind by dff2dffe
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// would prefer not to run 'opt_expr -mux_undef'
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// since that would lose information helpful for
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// efficient wide-mux inference
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match muxP
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if !ffP
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select muxP->type.in($mux)
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select port(muxP, \A).is_fully_undef()
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filter param(muxP, \WIDTH).as_int() == P_WIDTH
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filter port(muxP, \B) == port(dsp, \P).extract(0, P_WIDTH)
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select nusers(port(muxP, \B)) == 2
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optional
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endmatch
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if (ffY) {
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sigY = port(ffY, \Q);
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SigBit c = port(ffY, \CLK).as_bit();
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match ffY
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if muxP
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select ffY->type.in($dff, $dffe)
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select nusers(port(ffY, \D)) == 2
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index <SigSpec> port(ffY, \D) === port(muxP, \Y)
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endmatch
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code ffP clock
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if (ffY)
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ffP = ffY;
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if (ffP) {
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SigBit c = port(ffP, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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