mirror of https://github.com/YosysHQ/yosys.git
Added -try option to freduce pass
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@ -36,6 +36,7 @@ struct FreduceHelper
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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bool try_mode;
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ezDefaultSAT ez;
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SigMap sigmap;
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@ -60,8 +61,9 @@ struct FreduceHelper
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return xorshift32_state;
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}
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FreduceHelper(RTLIL::Design *design, RTLIL::Module *module) :
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design(design), module(module), sigmap(module), satgen(&ez, design, &sigmap), ce(module)
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FreduceHelper(RTLIL::Design *design, RTLIL::Module *module, bool try_mode) :
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design(design), module(module), try_mode(try_mode),
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sigmap(module), satgen(&ez, design, &sigmap), ce(module)
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{
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ct.setup_internals();
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ct.setup_stdcells();
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@ -72,17 +74,23 @@ struct FreduceHelper
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xorshift32();
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}
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void run_test(RTLIL::SigSpec test_vec)
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bool run_test(RTLIL::SigSpec test_vec)
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{
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ce.clear();
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ce.set(input_sigs, test_vec.as_const());
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for (auto &bit : nodes.bits) {
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RTLIL::SigSpec nodesig(bit.first, 1, bit.second), nodeval = nodesig;
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if (!ce.eval(nodeval))
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log_error("Evaluation of node %s failed!\n", log_signal(nodesig));
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if (!ce.eval(nodeval)) {
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if (!try_mode)
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log_error("Evaluation of node %s failed!\n", log_signal(nodesig));
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log("FAILED: Evaluation of node %s failed!\n", log_signal(nodesig));
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return false;
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}
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node_to_data[nodesig].bits.push_back(nodeval.as_const().bits.at(0));
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}
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return true;
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}
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void dump_node_data()
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@ -95,7 +103,7 @@ struct FreduceHelper
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log(" %-*s %s\n", max_node_len+5, log_signal(it.first), log_signal(it.second));
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}
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void check(RTLIL::SigSpec sig1, RTLIL::SigSpec sig2)
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bool check(RTLIL::SigSpec sig1, RTLIL::SigSpec sig2)
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{
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log(" performing SAT proof: %s == %s ->", log_signal(sig1), log_signal(sig2));
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@ -111,7 +119,8 @@ struct FreduceHelper
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testvect_sig.optimize();
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log(" failed: %s\n", log_signal(testvect_sig));
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test_vectors.push_back(testvect_sig.as_const());
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run_test(testvect_sig);
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if (!run_test(testvect_sig))
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return false;
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} else {
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log(" success.\n");
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if (!sig1.is_fully_const())
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@ -119,22 +128,26 @@ struct FreduceHelper
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if (!sig2.is_fully_const())
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node_result[sig2].append(sig1);
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}
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return true;
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}
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void analyze_const()
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bool analyze_const()
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{
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for (auto &it : node_to_data)
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{
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if (node_result.count(it.first))
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continue;
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if (it.second == RTLIL::Const(RTLIL::State::S0, it.second.bits.size()))
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check(it.first, RTLIL::SigSpec(RTLIL::State::S0));
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if (!check(it.first, RTLIL::SigSpec(RTLIL::State::S0)))
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return false;
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if (it.second == RTLIL::Const(RTLIL::State::S1, it.second.bits.size()))
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check(it.first, RTLIL::SigSpec(RTLIL::State::S1));
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if (!check(it.first, RTLIL::SigSpec(RTLIL::State::S1)))
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return false;
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}
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return true;
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}
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void analyze_alias()
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bool analyze_alias()
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{
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restart:
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std::map<RTLIL::Const, RTLIL::SigSpec> reverse_map;
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@ -158,9 +171,11 @@ struct FreduceHelper
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continue;
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if (node_to_data.at(sig1) != node_to_data.at(sig2))
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goto restart;
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check(it.second.chunks.at(i), it.second.chunks.at(j));
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if (!check(it.second.chunks.at(i), it.second.chunks.at(j)))
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return false;
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}
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}
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return true;
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}
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bool toproot_helper(RTLIL::SigSpec cursor, RTLIL::SigSpec stoplist, int level)
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@ -323,12 +338,16 @@ struct FreduceHelper
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}
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for (auto &test_vec : test_vectors)
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run_test(test_vec);
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if (!run_test(test_vec))
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return;
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// run the analysis and update design
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analyze_const();
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analyze_alias();
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if (!analyze_const())
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return;
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if (!analyze_alias())
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return;
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log(" input vector: %s\n", log_signal(input_sigs));
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for (auto &test_vec : test_vectors)
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@ -353,6 +372,10 @@ struct FreducePass : public Pass {
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log("equivialent, they are merged to one node and one of the redundant drivers is\n");
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log("removed.\n");
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log("\n");
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log(" -try\n");
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log(" do not issue an error when the analysis fails.\n");
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log(" (usually beacause of logic loops in the design)\n");
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log("\n");
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// log(" -enable_invert\n");
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// log(" also detect nodes that are inverse to each other.\n");
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// log("\n");
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@ -360,6 +383,7 @@ struct FreducePass : public Pass {
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool enable_invert = false;
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bool try_mode = false;
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log_header("Executing FREDUCE pass (perform functional reduction).\n");
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@ -369,6 +393,10 @@ struct FreducePass : public Pass {
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enable_invert = true;
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continue;
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}
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if (args[argidx] == "-try") {
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try_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -377,7 +405,7 @@ struct FreducePass : public Pass {
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{
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RTLIL::Module *module = mod_it.second;
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if (design->selected(module))
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FreduceHelper(design, module).run();
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FreduceHelper(design, module, try_mode).run();
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}
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}
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} FreducePass;
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