mirror of https://github.com/YosysHQ/yosys.git
Added tristate buffer support to iopadmap
This commit is contained in:
Clifford Wolf
parent
86add29072
commit
9647dc3c07
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@ -17,9 +17,8 @@
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -48,12 +47,23 @@ struct IopadmapPass : public Pass {
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log(" Map module input ports to the given cell type with the\n");
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log(" given output port name. if a 2nd portname is given, the\n");
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log(" signal is passed through the pad call, using the 2nd\n");
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log(" portname as input.\n");
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log(" portname as the port facing the module port.\n");
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log("\n");
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log(" -outpad <celltype> <portname>[:<portname>]\n");
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log(" -inoutpad <celltype> <portname>[:<portname>]\n");
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log(" Similar to -inpad, but for output and inout ports.\n");
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log("\n");
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log(" -toutpad <celltype> <portname>:<portname>[:<portname>]\n");
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log(" Merges $_TBUF_ cells into the output pad cell. This takes precedence\n");
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log(" over the other -outpad cell. The first portname is the enable input\n");
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log(" of the tristate driver.\n");
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log("\n");
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log(" -tinoutpad <celltype> <portname>:<portname>:<portname>[:<portname>]\n");
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log(" Merges $_TBUF_ cells into the inout pad cell. This takes precedence\n");
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log(" over the other -inoutpad cell. The first portname is the enable input\n");
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log(" of the tristate driver and the 2nd portname is the internal output\n");
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log(" buffering the external signal.\n");
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log("\n");
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log(" -widthparam <param_name>\n");
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log(" Use the specified parameter name to set the port width.\n");
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log("\n");
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@ -65,6 +75,8 @@ struct IopadmapPass : public Pass {
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log(" are wider. (the default behavior is to create word-wide\n");
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log(" buffers using -widthparam to set the word size on the cell.)\n");
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log("\n");
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log("Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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@ -73,6 +85,8 @@ struct IopadmapPass : public Pass {
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std::string inpad_celltype, inpad_portname, inpad_portname2;
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std::string outpad_celltype, outpad_portname, outpad_portname2;
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std::string inoutpad_celltype, inoutpad_portname, inoutpad_portname2;
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std::string toutpad_celltype, toutpad_portname, toutpad_portname2, toutpad_portname3;
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std::string tinoutpad_celltype, tinoutpad_portname, tinoutpad_portname2, tinoutpad_portname3, tinoutpad_portname4;
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std::string widthparam, nameparam;
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bool flag_bits = false;
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@ -98,6 +112,21 @@ struct IopadmapPass : public Pass {
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split_portname_pair(inoutpad_portname, inoutpad_portname2);
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continue;
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}
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if (arg == "-toutpad" && argidx+2 < args.size()) {
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toutpad_celltype = args[++argidx];
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toutpad_portname = args[++argidx];
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split_portname_pair(toutpad_portname, toutpad_portname2);
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split_portname_pair(toutpad_portname2, toutpad_portname3);
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continue;
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}
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if (arg == "-tinoutpad" && argidx+2 < args.size()) {
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tinoutpad_celltype = args[++argidx];
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tinoutpad_portname = args[++argidx];
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split_portname_pair(tinoutpad_portname, tinoutpad_portname2);
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split_portname_pair(tinoutpad_portname2, tinoutpad_portname3);
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split_portname_pair(tinoutpad_portname3, tinoutpad_portname4);
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continue;
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}
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if (arg == "-widthparam" && argidx+1 < args.size()) {
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widthparam = args[++argidx];
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continue;
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@ -116,12 +145,132 @@ struct IopadmapPass : public Pass {
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for (auto module : design->selected_modules())
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{
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dict<IdString, pool<int>> skip_wires;
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if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
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{
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SigMap sigmap(module);
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dict<SigBit, pair<IdString, pool<IdString>>> tbuf_bits;
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for (auto cell : module->cells())
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if (cell->type == "$_TBUF_") {
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SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
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tbuf_bits[bit].first = cell->name;
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}
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for (auto cell : module->cells())
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for (auto port : cell->connections())
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for (auto bit : sigmap(port.second))
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if (tbuf_bits.count(bit))
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tbuf_bits.at(bit).second.insert(cell->name);
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for (auto wire : module->selected_wires())
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{
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if (!wire->port_output)
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continue;
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for (int i = 0; i < GetSize(wire); i++)
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{
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SigBit wire_bit(wire, i);
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SigBit mapped_wire_bit = sigmap(wire_bit);
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if (tbuf_bits.count(mapped_wire_bit) == 0)
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continue;
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auto &tbuf_cache = tbuf_bits.at(mapped_wire_bit);
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Cell *tbuf_cell = module->cell(tbuf_cache.first);
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if (tbuf_cell == nullptr)
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continue;
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SigBit en_sig = tbuf_cell->getPort("\\E").as_bit();
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SigBit data_sig = tbuf_cell->getPort("\\A").as_bit();
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if (wire->port_input && !tinoutpad_celltype.empty())
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{
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log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str());
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Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(tinoutpad_celltype));
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Wire *owire = module->addWire(NEW_ID);
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cell->setPort(RTLIL::escape_id(tinoutpad_portname), en_sig);
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cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire);
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cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig);
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cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit);
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cell->attributes["\\keep"] = RTLIL::Const(1);
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for (auto cn : tbuf_cache.second) {
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auto c = module->cell(cn);
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if (c == nullptr)
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continue;
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for (auto port : c->connections()) {
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SigSpec sig = port.second;
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bool newsig = false;
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for (auto &bit : sig)
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if (sigmap(bit) == mapped_wire_bit) {
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bit = owire;
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newsig = true;
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}
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if (newsig)
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c->setPort(port.first, sig);
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}
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}
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module->remove(tbuf_cell);
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skip_wires[wire->name].insert(i);
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continue;
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}
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if (!wire->port_input && !toutpad_celltype.empty())
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{
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log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str());
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Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(toutpad_celltype));
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cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig);
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cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig);
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cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit);
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cell->attributes["\\keep"] = RTLIL::Const(1);
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for (auto cn : tbuf_cache.second) {
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auto c = module->cell(cn);
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if (c == nullptr)
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continue;
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for (auto port : c->connections()) {
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SigSpec sig = port.second;
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bool newsig = false;
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for (auto &bit : sig)
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if (sigmap(bit) == mapped_wire_bit) {
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bit = data_sig;
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newsig = true;
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}
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if (newsig)
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c->setPort(port.first, sig);
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}
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}
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module->remove(tbuf_cell);
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skip_wires[wire->name].insert(i);
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continue;
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}
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}
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}
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}
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for (auto wire : module->selected_wires())
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{
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if (!wire->port_id)
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continue;
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std::string celltype, portname, portname2;
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pool<int> skip_bit_indices;
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if (skip_wires.count(wire->name)) {
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if (!flag_bits)
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continue;
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skip_bit_indices = skip_wires.at(wire->name);
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}
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if (wire->port_input && !wire->port_output) {
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if (inpad_celltype.empty()) {
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@ -170,6 +319,14 @@ struct IopadmapPass : public Pass {
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{
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for (int i = 0; i < wire->width; i++)
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{
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if (skip_bit_indices.count(i)) {
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if (wire->port_output)
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module->connect(SigSpec(new_wire, i), SigSpec(wire, i));
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else
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module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
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continue;
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}
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RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
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cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
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if (!portname2.empty())
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