mirror of https://github.com/YosysHQ/yosys.git
Add handling of constant reset signals to opt_rmdff
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48b2b376d0
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@ -186,7 +186,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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goto delete_dff;
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}
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if (sig_d == sig_q && (!sig_r.size() || !has_init || val_init == val_rv)) {
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if (sig_d == sig_q && (sig_r.empty() || !has_init || val_init == val_rv)) {
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if (sig_r.size())
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mod->connect(sig_q, val_rv);
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if (has_init)
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@ -194,6 +194,28 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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goto delete_dff;
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}
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if (!sig_r.empty() && sig_r.is_fully_const())
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{
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if (sig_r == val_rp || sig_r.is_fully_undef()) {
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mod->connect(sig_q, val_rv);
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goto delete_dff;
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}
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log("Removing unused reset from %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod));
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if (dff->type == "$adff") {
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dff->type = "$dff";
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dff->unsetPort("\\ARST");
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dff->unsetParam("\\ARST_POLARITY");
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dff->unsetParam("\\ARST_VALUE");
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return true;
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}
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log_assert(dff->type.substr(0,6) == "$_DFF_");
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dff->type = stringf("$_DFF_%c_", + dff->type[6]);
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dff->unsetPort("\\R");
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}
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return false;
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delete_dff:
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