mirror of https://github.com/YosysHQ/yosys.git
Fix indenting and log messages in code merged from opt_compare_pr
This commit is contained in:
Clifford Wolf
parent
19a980277f
commit
ffbe8d41f3
|
|
@ -258,29 +258,30 @@ bool is_one_or_minus_one(const Const &value, bool is_signed, bool &is_negative)
|
|||
|
||||
return last_bit_one;
|
||||
}
|
||||
//if the signal has only one bit set, return the index of that bit.
|
||||
//otherwise return -1
|
||||
int get_onehot_bit_index(RTLIL::SigSpec signal){
|
||||
if(!signal.is_fully_const())
|
||||
return -1;
|
||||
bool bit_set = false;
|
||||
int bit_index = 0;
|
||||
int i = 0;
|
||||
for(auto bit: signal.bits()){
|
||||
if(bit == RTLIL::State::S1){
|
||||
if(bit_set)
|
||||
return -1;
|
||||
bit_index = i;
|
||||
bit_set = true;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
if(bit_set){
|
||||
return bit_index;
|
||||
}else{
|
||||
return -1;
|
||||
}
|
||||
|
||||
// if the signal has only one bit set, return the index of that bit.
|
||||
// otherwise return -1
|
||||
int get_onehot_bit_index(RTLIL::SigSpec signal)
|
||||
{
|
||||
int bit_index = -1;
|
||||
|
||||
for (int i = 0; i < GetSize(signal); i++)
|
||||
{
|
||||
if (signal[i] == RTLIL::State::S0)
|
||||
continue;
|
||||
|
||||
if (signal[i] != RTLIL::State::S1)
|
||||
return -1;
|
||||
|
||||
if (bit_index != -1)
|
||||
return -1;
|
||||
|
||||
bit_index = i;
|
||||
}
|
||||
|
||||
return bit_index;
|
||||
}
|
||||
|
||||
void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool clkinv)
|
||||
{
|
||||
if (!design->selected(module))
|
||||
|
|
@ -1188,86 +1189,103 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
}
|
||||
}
|
||||
}
|
||||
//replace a <0 or a >=0 with the top bit of a
|
||||
if(do_fine && (cell->type == "$lt" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$le"))
|
||||
{
|
||||
bool is_lt = false; //used to decide whether the signal needs to be negated
|
||||
RTLIL::SigSpec sigVar; //references the variable signal in the comparison
|
||||
RTLIL::SigSpec sigConst; //references the constant signal in the comparison
|
||||
//note that this signal must be constant for the optimization
|
||||
//to take place, but it is not checked beforehand.
|
||||
//If new passes are added, this signal must be checked for const-ness
|
||||
int width; //width of the variable port
|
||||
bool var_signed;
|
||||
if(cell->type == "$lt" || cell->type == "$ge"){
|
||||
is_lt = cell->type == "$lt" ? 1 : 0;
|
||||
sigVar = cell->getPort("\\A");
|
||||
sigConst = cell->getPort("\\B");
|
||||
width = cell->parameters["\\A_WIDTH"].as_int();
|
||||
var_signed = cell->parameters["\\A_SIGNED"].as_bool();
|
||||
}
|
||||
if(cell->type == "$gt" || cell->type == "$le"){
|
||||
is_lt = cell->type == "$gt" ? 1 : 0;
|
||||
sigVar = cell->getPort("\\B");
|
||||
sigConst = cell->getPort("\\A");
|
||||
width = cell->parameters["\\B_WIDTH"].as_int();
|
||||
var_signed = cell->parameters["\\B_SIGNED"].as_bool();
|
||||
}
|
||||
//replace a(signed) < 0 with the high bit of a
|
||||
if(sigConst.is_fully_const() && sigConst.is_fully_zero() && var_signed == true){
|
||||
RTLIL::SigSpec a_prime(RTLIL::State::S0, cell->parameters["\\Y_WIDTH"].as_int());
|
||||
a_prime[0] = sigVar[width-1];
|
||||
if(is_lt){
|
||||
log("Optimizing a < 0 with a[%d]\n",width - 1);
|
||||
module->connect(cell->getPort("\\Y"), a_prime);
|
||||
module->remove(cell);
|
||||
}
|
||||
else{
|
||||
log("Optimizing a >= 0 with ~a[%d]\n",width - 1);
|
||||
module->addNot(NEW_ID, a_prime, cell->getPort("\\Y"));
|
||||
module->remove(cell);
|
||||
}
|
||||
did_something = true;
|
||||
goto next_cell;
|
||||
}
|
||||
else if(sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false){
|
||||
int const_bit_set = get_onehot_bit_index(sigConst);
|
||||
if(sigConst.is_fully_zero()){
|
||||
RTLIL::SigSpec a_prime(RTLIL::State::S0,1);
|
||||
if(is_lt){
|
||||
log("replacing a(unsigned) < 0 with constant false\n");
|
||||
a_prime[0] = RTLIL::State::S0;
|
||||
}
|
||||
else{
|
||||
log("replacing a(unsigned) >= 0 with constant true\n");
|
||||
a_prime[0] = RTLIL::State::S1;
|
||||
}
|
||||
module->connect(cell->getPort("\\Y"), a_prime);
|
||||
module->remove(cell);
|
||||
did_something = true;
|
||||
goto next_cell;
|
||||
}
|
||||
|
||||
else if(const_bit_set >= 0){ //if b has only 1 bit set
|
||||
int bit_set = const_bit_set;
|
||||
RTLIL::SigSpec a_prime(RTLIL::State::S0,width-bit_set);
|
||||
for(int i = bit_set; i < width; i++){
|
||||
a_prime[i-bit_set] = sigVar[i];
|
||||
}
|
||||
if(is_lt){
|
||||
log("replacing a < %d with !a[%d:%d]\n",sigConst.as_int(false),width-1,bit_set);
|
||||
module->addLogicNot(NEW_ID, a_prime,cell->getPort("\\Y"));
|
||||
}
|
||||
else{
|
||||
log("replacing a >= %d with |a[%d:%d]\n",sigConst.as_int(false),width-1,bit_set);
|
||||
module->addReduceOr(NEW_ID, a_prime,cell->getPort("\\Y"));
|
||||
}
|
||||
module->remove(cell);
|
||||
did_something = true;
|
||||
goto next_cell;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// replace a<0 or a>=0 with the top bit of a
|
||||
if (do_fine && (cell->type == "$lt" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$le"))
|
||||
{
|
||||
//used to decide whether the signal needs to be negated
|
||||
bool is_lt = false;
|
||||
|
||||
//references the variable signal in the comparison
|
||||
RTLIL::SigSpec sigVar;
|
||||
|
||||
//references the constant signal in the comparison
|
||||
RTLIL::SigSpec sigConst;
|
||||
|
||||
// note that this signal must be constant for the optimization
|
||||
// to take place, but it is not checked beforehand.
|
||||
// If new passes are added, this signal must be checked for const-ness
|
||||
|
||||
//width of the variable port
|
||||
int width;
|
||||
|
||||
bool var_signed;
|
||||
|
||||
if (cell->type == "$lt" || cell->type == "$ge") {
|
||||
is_lt = cell->type == "$lt" ? 1 : 0;
|
||||
sigVar = cell->getPort("\\A");
|
||||
sigConst = cell->getPort("\\B");
|
||||
width = cell->parameters["\\A_WIDTH"].as_int();
|
||||
var_signed = cell->parameters["\\A_SIGNED"].as_bool();
|
||||
} else
|
||||
if (cell->type == "$gt" || cell->type == "$le") {
|
||||
is_lt = cell->type == "$gt" ? 1 : 0;
|
||||
sigVar = cell->getPort("\\B");
|
||||
sigConst = cell->getPort("\\A");
|
||||
width = cell->parameters["\\B_WIDTH"].as_int();
|
||||
var_signed = cell->parameters["\\B_SIGNED"].as_bool();
|
||||
}
|
||||
|
||||
// replace a(signed) < 0 with the high bit of a
|
||||
if (sigConst.is_fully_const() && sigConst.is_fully_zero() && var_signed == true)
|
||||
{
|
||||
RTLIL::SigSpec a_prime(RTLIL::State::S0, cell->parameters["\\Y_WIDTH"].as_int());
|
||||
a_prime[0] = sigVar[width - 1];
|
||||
if (is_lt) {
|
||||
log("Replacing %s cell `%s' (implementing X<0) with X[%d]: %s\n",
|
||||
log_id(cell->type), log_id(cell), width-1, log_signal(a_prime));
|
||||
module->connect(cell->getPort("\\Y"), a_prime);
|
||||
module->remove(cell);
|
||||
} else {
|
||||
log("Replacing %s cell `%s' (implementing X>=0) with ~X[%d]: %s\n",
|
||||
log_id(cell->type), log_id(cell), width-1, log_signal(a_prime));
|
||||
module->addNot(NEW_ID, a_prime, cell->getPort("\\Y"));
|
||||
module->remove(cell);
|
||||
}
|
||||
did_something = true;
|
||||
goto next_cell;
|
||||
} else
|
||||
if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false)
|
||||
{
|
||||
if (sigConst.is_fully_zero()) {
|
||||
RTLIL::SigSpec a_prime(RTLIL::State::S0, 1);
|
||||
if (is_lt) {
|
||||
log("Replacing %s cell `%s' (implementing unsigned X<0) with constant false.\n",
|
||||
log_id(cell->type), log_id(cell));
|
||||
a_prime[0] = RTLIL::State::S0;
|
||||
} else {
|
||||
log("Replacing %s cell `%s' (implementing unsigned X>=0) with constant true.\n",
|
||||
log_id(cell->type), log_id(cell));
|
||||
a_prime[0] = RTLIL::State::S1;
|
||||
}
|
||||
module->connect(cell->getPort("\\Y"), a_prime);
|
||||
module->remove(cell);
|
||||
did_something = true;
|
||||
goto next_cell;
|
||||
}
|
||||
|
||||
int const_bit_set = get_onehot_bit_index(sigConst);
|
||||
if (const_bit_set >= 0) {
|
||||
int bit_set = const_bit_set;
|
||||
RTLIL::SigSpec a_prime(RTLIL::State::S0, width - bit_set);
|
||||
for (int i = bit_set; i < width; i++) {
|
||||
a_prime[i - bit_set] = sigVar[i];
|
||||
}
|
||||
if (is_lt) {
|
||||
log("Replacing %s cell `%s' (implementing unsigned X<%s) with !X[%d:%d]: %s.\n",
|
||||
log_id(cell->type), log_id(cell), log_signal(sigConst), width - 1, bit_set, log_signal(a_prime));
|
||||
module->addLogicNot(NEW_ID, a_prime, cell->getPort("\\Y"));
|
||||
} else {
|
||||
log("Replacing %s cell `%s' (implementing unsigned X>=%s) with |X[%d:%d]: %s.\n",
|
||||
log_id(cell->type), log_id(cell), log_signal(sigConst), width - 1, bit_set, log_signal(a_prime));
|
||||
module->addReduceOr(NEW_ID, a_prime, cell->getPort("\\Y"));
|
||||
}
|
||||
module->remove(cell);
|
||||
did_something = true;
|
||||
goto next_cell;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
next_cell:;
|
||||
#undef ACTION_DO
|
||||
|
|
|
|||
Loading…
Reference in New Issue