mirror of https://github.com/YosysHQ/yosys.git
Added "opt_const -mux_undef"
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a3d94bf888
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@ -42,7 +42,7 @@ void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, st
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did_something = true;
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}
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void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x)
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void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef)
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{
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if (!design->selected(module))
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return;
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@ -139,8 +139,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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cell->connections.erase("\\S");
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goto next_cell;
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}
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if (input.match("11 ")) ACTION_DO_Y(1);
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if (input.match("00 ")) ACTION_DO_Y(0);
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if (input.match("** ")) ACTION_DO_Y(x);
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if (input.match("01*")) ACTION_DO_Y(x);
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if (input.match("10*")) ACTION_DO_Y(x);
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if (mux_undef) {
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if (input.match("* ")) ACTION_DO("\\Y", input.extract(1, 1));
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if (input.match(" * ")) ACTION_DO("\\Y", input.extract(2, 1));
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if (input.match(" *")) ACTION_DO("\\Y", input.extract(2, 1));
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}
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}
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if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex")
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@ -216,6 +224,51 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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}
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if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) {
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RTLIL::SigSpec new_a, new_b, new_s;
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int width = cell->connections.at("\\A").width;
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if ((cell->connections.at("\\A").is_fully_undef() && cell->connections.at("\\B").is_fully_undef()) ||
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cell->connections.at("\\S").is_fully_undef()) {
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replace_cell(module, cell, "mux undef", "\\Y", cell->connections.at("\\A"));
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goto next_cell;
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}
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for (int i = 0; i < cell->connections.at("\\S").width; i++) {
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RTLIL::SigSpec old_b = cell->connections.at("\\B").extract(i*width, width);
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RTLIL::SigSpec old_s = cell->connections.at("\\S").extract(i, 1);
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if (old_b.is_fully_undef() || old_s.is_fully_undef())
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continue;
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new_b.append(old_b);
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new_s.append(old_s);
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}
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new_a = cell->connections.at("\\A");
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if (new_a.is_fully_undef() && new_s.width > 0) {
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new_a = new_b.extract((new_s.width-1)*width, width);
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new_b = new_b.extract(0, (new_s.width-1)*width);
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new_s = new_s.extract(0, new_s.width-1);
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}
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if (new_s.width == 0) {
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replace_cell(module, cell, "mux undef", "\\Y", new_a);
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goto next_cell;
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}
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if (new_a == RTLIL::SigSpec(RTLIL::State::S0) && new_b == RTLIL::SigSpec(RTLIL::State::S1)) {
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replace_cell(module, cell, "mux undef", "\\Y", new_s);
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goto next_cell;
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}
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if (cell->connections.at("\\S").width != new_s.width) {
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cell->connections.at("\\A") = new_a;
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cell->connections.at("\\B") = new_b;
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cell->connections.at("\\S") = new_s;
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if (new_s.width > 1) {
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cell->type = "$pmux";
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cell->parameters["\\S_WIDTH"] = new_s.width;
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} else {
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cell->type = "$mux";
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cell->parameters.erase("\\S_WIDTH");
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}
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did_something = true;
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}
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}
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#define FOLD_1ARG_CELL(_t) \
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if (cell->type == "$" #_t) { \
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RTLIL::SigSpec a = cell->connections["\\A"]; \
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@ -312,25 +365,38 @@ struct OptConstPass : public Pass {
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_const [selection]\n");
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log(" opt_const [options] [selection]\n");
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log("\n");
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log("This pass performs const folding on internal cell types with constant inputs.\n");
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log("\n");
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log(" -mux_undef\n");
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log(" remove 'undef' inputs from $mux, $pmux and $_MUX_ cells\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool mux_undef = false;
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log_header("Executing OPT_CONST pass (perform const folding).\n");
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log_push();
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extra_args(args, 1, design);
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-mux_undef") {
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mux_undef = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto &mod_it : design->modules)
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do {
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do {
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did_something = false;
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replace_const_cells(design, mod_it.second, false);
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replace_const_cells(design, mod_it.second, false, mux_undef);
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} while (did_something);
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replace_const_cells(design, mod_it.second, true);
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replace_const_cells(design, mod_it.second, true, mux_undef);
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} while (did_something);
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log_pop();
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