mirror of https://github.com/YosysHQ/yosys.git
Added "nlutmap -assert"
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@ -26,6 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
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struct NlutmapConfig
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{
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vector<int> luts;
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bool assert_mode = false;
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};
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struct NlutmapWorker
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@ -116,6 +117,12 @@ struct NlutmapWorker
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available_luts.back() += n_luts;
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}
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if (config.assert_mode) {
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for (auto cell : module->cells())
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if (cell->type == "$lut" && !mapped_cells.count(cell))
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log_error("Insufficient number of LUTs to map all logic cells!\n");
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}
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run_abc(0);
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}
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};
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@ -135,6 +142,9 @@ struct NlutmapPass : public Pass {
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log(" The number of LUTs with 1, 2, 3, ... inputs that are\n");
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log(" available in the target architecture.\n");
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log("\n");
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log(" -assert\n");
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log(" Create an error if not all logic can be mapped\n");
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log("\n");
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log("Excess logic that does not fit into the specified LUTs is mapped back\n");
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log("to generic logic gates ($_AND_, etc.).\n");
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log("\n");
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@ -156,6 +166,10 @@ struct NlutmapPass : public Pass {
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config.luts.push_back(atoi(token.c_str()));
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continue;
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}
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if (args[argidx] == "-assert") {
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config.assert_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -167,9 +167,9 @@ struct SynthGreenPAK4Pass : public ScriptPass
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if (check_label("map_luts"))
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{
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if (help_mode || part == "SLG46140V") run("nlutmap -luts 0,6,8,2", " (for -part SLG46140V)");
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if (help_mode || part == "SLG46620V") run("nlutmap -luts 2,8,16,2", "(for -part SLG46620V)");
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if (help_mode || part == "SLG46621V") run("nlutmap -luts 2,8,16,2", "(for -part SLG46621V)");
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if (help_mode || part == "SLG46140V") run("nlutmap -assert -luts 0,6,8,2", " (for -part SLG46140V)");
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if (help_mode || part == "SLG46620V") run("nlutmap -assert -luts 2,8,16,2", "(for -part SLG46620V)");
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if (help_mode || part == "SLG46621V") run("nlutmap -assert -luts 2,8,16,2", "(for -part SLG46621V)");
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run("clean");
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}
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