mirror of https://github.com/YosysHQ/yosys.git
Bugfix in hierarchy blackbox module port width handling
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@ -621,8 +621,9 @@ struct HierarchyPass : public Pass {
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}
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std::set<Module*> blackbox_derivatives;
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std::vector<Module*> design_modules = design->modules();
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for (auto module : design->modules())
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for (auto module : design_modules)
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for (auto cell : module->cells())
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{
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Module *m = design->module(cell->type);
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