mirror of https://github.com/YosysHQ/yosys.git
Added "flatten" pass
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@ -31,7 +31,7 @@ static void apply_prefix(std::string prefix, std::string &id)
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if (id[0] == '\\')
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id = prefix + "." + id.substr(1);
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else
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id = prefix + "." + id;
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id = "$techmap" + prefix + "." + id;
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}
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static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
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@ -280,3 +280,43 @@ struct TechmapPass : public Pass {
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}
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} TechmapPass;
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struct FlattenPass : public Pass {
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FlattenPass() : Pass("flatten", "flatten design") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" flatten [selection]\n");
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log("\n");
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log("This pass flattens the design by replacing cells by their implementation. This\n");
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log("pass is very simmilar to the 'techmap' pass. The only difference is that this\n");
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log("pass is using the current design as mapping library.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing FLATTEN pass (flatten design).\n");
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log_push();
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extra_args(args, 1, design);
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std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
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for (auto &it : design->modules)
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celltypeMap[it.first].insert(it.first);
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bool did_something = true;
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std::set<RTLIL::Cell*> handled_cells;
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while (did_something) {
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did_something = false;
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for (auto &mod_it : design->modules)
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if (techmap_module(design, mod_it.second, design, handled_cells, celltypeMap))
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did_something = true;
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}
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log("No more expansions possible.\n");
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techmap_cache.clear();
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techmap_fail_cache.clear();
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log_pop();
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}
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} FlattenPass;
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