mirror of https://github.com/YosysHQ/yosys.git
Fixed $eq/$ne bitwise optimization in opt_const
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@ -146,16 +146,15 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (cell->type == "$eq" || cell->type == "$ne")
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{
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if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
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int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
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cell->connections["\\A"].extend(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
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cell->connections["\\B"].extend(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
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cell->parameters["\\A_WIDTH"] = width;
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cell->parameters["\\B_WIDTH"] = width;
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}
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RTLIL::SigSpec a = cell->connections["\\A"];
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RTLIL::SigSpec b = cell->connections["\\B"];
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if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
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int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
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a.extend(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
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b.extend(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
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}
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RTLIL::SigSpec new_a, new_b;
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a.expand(), b.expand();
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@ -179,7 +178,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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if (new_a.width == 0) {
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replace_cell(module, cell, "empty", "\\Y", RTLIL::SigSpec(cell->type == "$eq" ? RTLIL::State::S1 : RTLIL::State::S0));
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RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type == "$eq" ? RTLIL::State::S1 : RTLIL::State::S0);
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new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
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replace_cell(module, cell, "empty", "\\Y", new_y);
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goto next_cell;
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}
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}
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