mirror of https://github.com/YosysHQ/yosys.git
Revision to expose option in setundef pass
Corrects indentation Simplifications and corrections
This commit is contained in:
Aman Goel
parent
61f002c908
commit
83b41260f6
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@ -33,67 +33,32 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
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static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output)
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{
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RTLIL::Wire *wire = NULL;
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name = RTLIL::escape_id(name);
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RTLIL::Wire *wire = NULL;
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name = RTLIL::escape_id(name);
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if (module->count_id(name) != 0)
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{
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if (module->wires_.count(name) > 0)
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wire = module->wires_.at(name);
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if (module->count_id(name) != 0)
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{
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log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str());
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name += "$";
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return add_wire(module, name, width, flag_input, flag_output);
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}
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else
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{
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wire = module->addWire(name, width);
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wire->port_input = flag_input;
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wire->port_output = flag_output;
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if (wire != NULL && wire->width != width)
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wire = NULL;
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if (flag_input || flag_output) {
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wire->port_id = module->wires_.size();
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module->fixup_ports();
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}
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if (wire != NULL && wire->port_input != flag_input)
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wire = NULL;
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log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
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}
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if (wire != NULL && wire->port_output != flag_output)
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wire = NULL;
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if (wire == NULL) {
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return wire;
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log_cmd_error("Found incompatible object %s with same name in module %s!\n", name.c_str(), module->name.c_str());
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}
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log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str());
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}
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else
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{
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wire = module->addWire(name, width);
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wire->port_input = flag_input;
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wire->port_output = flag_output;
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if (flag_input || flag_output) {
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wire->port_id = module->wires_.size();
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module->fixup_ports();
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}
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log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
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}
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if (!flag_global)
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return wire;
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for (auto &it : module->cells_)
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{
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if (design->modules_.count(it.second->type) == 0)
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continue;
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RTLIL::Module *mod = design->modules_.at(it.second->type);
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if (!design->selected_whole_module(mod->name))
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continue;
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if (mod->get_bool_attribute("\\blackbox"))
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continue;
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if (it.second->hasPort(name))
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continue;
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it.second->setPort(name, wire);
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log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
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}
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return wire;
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return wire;
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}
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struct SetundefWorker
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@ -262,100 +227,104 @@ struct SetundefPass : public Pass {
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if (!module->processes.empty())
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log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n");
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if (expose_mode) {
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SigMap sigmap(module);
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dict<SigBit, bool> wire_drivers;
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pool<SigBit> used_wires;
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SigPool undriven_signals;
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if (expose_mode)
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{
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SigMap sigmap(module);
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dict<SigBit, bool> wire_drivers;
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pool<SigBit> used_wires;
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SigPool undriven_signals;
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for (auto cell : module->cells())
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for (auto &conn : cell->connections()) {
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SigSpec sig = sigmap(conn.second);
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if (cell->input(conn.first))
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for (auto bit : sig)
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if (bit.wire) {
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used_wires.insert(bit);
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}
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if (cell->output(conn.first))
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for (int i = 0; i < GetSize(sig); i++) {
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if (sig[i].wire)
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wire_drivers[sig[i]] = true;
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}
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}
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for (auto cell : module->cells())
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for (auto &conn : cell->connections()) {
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SigSpec sig = sigmap(conn.second);
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if (cell->input(conn.first))
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for (auto bit : sig)
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if (bit.wire)
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used_wires.insert(bit);
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if (cell->output(conn.first))
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for (int i = 0; i < GetSize(sig); i++)
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if (sig[i].wire)
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wire_drivers[sig[i]] = true;
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}
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for (auto wire : module->wires()) {
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if (wire->port_input) {
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SigSpec sig = sigmap(wire);
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for (int i = 0; i < GetSize(sig); i++)
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wire_drivers[sig[i]] = true;
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}
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if (wire->port_output)
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for (auto bit : sigmap(wire))
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if (bit.wire) used_wires.insert(bit);
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}
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for (auto wire : module->wires()) {
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if (wire->port_input) {
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SigSpec sig = sigmap(wire);
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for (int i = 0; i < GetSize(sig); i++)
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wire_drivers[sig[i]] = true;
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}
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if (wire->port_output) {
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SigSpec sig = sigmap(wire);
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for (auto bit : sig)
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if (bit.wire)
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used_wires.insert(bit);
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}
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}
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pool<RTLIL::Wire*> undriven_wires;
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for (auto bit : used_wires) {
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if (!wire_drivers.count(bit)) {
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undriven_wires.insert(bit.wire);
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}
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}
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pool<RTLIL::Wire*> undriven_wires;
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for (auto bit : used_wires)
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if (!wire_drivers.count(bit))
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undriven_wires.insert(bit.wire);
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for (auto &it : undriven_wires)
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undriven_signals.add(sigmap(it));
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for (auto &it : undriven_wires)
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undriven_signals.add(sigmap(it));
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for (auto &it : undriven_wires)
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if (it->port_input)
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undriven_signals.del(sigmap(it));
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for (auto &it : undriven_wires)
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if (it->port_input)
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undriven_signals.del(sigmap(it));
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CellTypes ct(design);
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for (auto &it : module->cells_)
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for (auto &conn : it.second->connections())
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if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
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undriven_signals.del(sigmap(conn.second));
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CellTypes ct(design);
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for (auto &it : module->cells_)
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for (auto &conn : it.second->connections())
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if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
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undriven_signals.del(sigmap(conn.second));
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RTLIL::SigSpec sig = undriven_signals.export_all();
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for (auto &c : sig.chunks()) {
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RTLIL::Wire * wire;
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if (c.wire->width == c.width) {
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wire = c.wire;
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wire->port_input = true;
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}
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else {
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string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]";
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wire = add_wire(design, module, name, c.width, true, false, false);
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module->connect(RTLIL::SigSig(c, wire));
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}
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log("Exposing undriven wire %s as input.\n", wire->name.c_str());
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}
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module->fixup_ports();
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continue;
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}
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else {
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SigMap sigmap(module);
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SigPool undriven_signals;
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RTLIL::SigSpec sig = undriven_signals.export_all();
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for (auto &c : sig.chunks()) {
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RTLIL::Wire * wire;
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if (c.wire->width == c.width) {
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wire = c.wire;
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wire->port_input = true;
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} else {
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string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]";
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wire = add_wire(module, name, c.width, true, false);
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module->connect(RTLIL::SigSig(c, wire));
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}
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log("Exposing undriven wire %s as input.\n", wire->name.c_str());
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}
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module->fixup_ports();
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}
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else
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{
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SigMap sigmap(module);
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SigPool undriven_signals;
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for (auto &it : module->wires_)
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undriven_signals.add(sigmap(it.second));
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for (auto &it : module->wires_)
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undriven_signals.add(sigmap(it.second));
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for (auto &it : module->wires_)
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if (it.second->port_input)
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undriven_signals.del(sigmap(it.second));
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for (auto &it : module->wires_)
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if (it.second->port_input)
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undriven_signals.del(sigmap(it.second));
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CellTypes ct(design);
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for (auto &it : module->cells_)
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for (auto &conn : it.second->connections())
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if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
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undriven_signals.del(sigmap(conn.second));
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CellTypes ct(design);
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for (auto &it : module->cells_)
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for (auto &conn : it.second->connections())
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if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
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undriven_signals.del(sigmap(conn.second));
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RTLIL::SigSpec sig = undriven_signals.export_all();
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for (auto &c : sig.chunks()) {
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RTLIL::SigSpec bits;
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for (int i = 0; i < c.width; i++)
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bits.append(worker.next_bit());
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module->connect(RTLIL::SigSig(c, bits));
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}
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}
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RTLIL::SigSpec sig = undriven_signals.export_all();
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for (auto &c : sig.chunks()) {
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RTLIL::SigSpec bits;
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if (worker.next_bit_mode == MODE_ANYSEQ)
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bits = module->Anyseq(NEW_ID, c.width);
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else if (worker.next_bit_mode == MODE_ANYCONST)
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bits = module->Anyconst(NEW_ID, c.width);
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else
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for (int i = 0; i < c.width; i++)
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bits.append(worker.next_bit());
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module->connect(RTLIL::SigSig(c, bits));
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}
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}
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}
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if (init_mode)
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