riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

using [i] to access individual bits of SigSpec and merging bits into a tmp Sig before setting the port to new signal

This commit is contained in:
rafaeltp 2018-10-21 11:32:44 -07:00
parent 7b964bfb83
commit f8b97e21f3
1 changed files with 11 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
passes/equiv/equiv_make.cc
View File

@ -298,20 +298,21 @@ struct EquivMakeWorker
SigSpec new_sig = rd_signal_map(old_sig);
if(old_sig != new_sig) {
for (auto &old_bit : old_sig.bits()) {
SigBit new_bit = new_sig.bits()[old_bit.offset];
SigSpec tmp_sig = old_sig;
for (int i = 0; i < GetSize(old_sig); i++) {
SigBit old_bit = old_sig[i], new_bit = new_sig[i];
visited_cells.clear();
if (old_bit != new_bit) {
if (check_signal_in_fanout(visited_cells, old_bit, new_bit))
continue;
if (check_signal_in_fanout(visited_cells, old_bit, new_bit))
continue;
log("Changing input %s of cell %s (%s): %s -> %s\n",
log_id(conn.first), log_id(c), log_id(c->type),
log_signal(old_bit), log_signal(new_bit));
c->setPort(conn.first, new_bit);
}
log("Changing input %s of cell %s (%s): %s -> %s\n",
log_id(conn.first), log_id(c), log_id(c->type),
log_signal(old_bit), log_signal(new_bit));
tmp_sig[i] = new_bit;
}
c->setPort(conn.first, tmp_sig);
}
}