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Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp

This commit is contained in:
Eddie Hung 2019-07-19 14:03:34 -07:00
parent 8791e0caac c926eeb43a
commit e87916b7eb
3 changed files with 29 additions and 5 deletions
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1
kernel/rtlil.h
View File

@ -818,6 +818,7 @@ public:
operator std::vector<RTLIL::SigChunk>() const { return chunks(); }
operator std::vector<RTLIL::SigBit>() const { return bits(); }
RTLIL::SigBit at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }
unsigned int hash() const { if (!hash_) updhash(); return hash_; };

8
passes/opt/wreduce.cc
View File

@ -366,13 +366,13 @@ struct WreduceWorker
}
if (cell->type.in("$add", "$sub")) {
SigSpec A = cell->getPort("\\A");
SigSpec B = cell->getPort("\\B");
SigSpec A = mi.sigmap(cell->getPort("\\A"));
SigSpec B = mi.sigmap(cell->getPort("\\B"));
bool sub = cell->type == "$sub";
int i;
for (i = 0; i < GetSize(sig); i++) {
if (B[i] != S0 && (sub || A[i] != S0))
if (B.at(i, Sx) != S0 && (sub || A.at(i, Sx) != S0))
break;
if (B[i] == S0)
module->connect(sig[i], A[i]);
@ -395,7 +395,7 @@ struct WreduceWorker
}
if (bits_removed) {
log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
log("Removed %d bits (of %d) from port Y of cell %s.%s (%s).\n",
bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type));
cell->setPort("\\Y", sig);
did_something = true;

25
tests/various/wreduce.ys
View File

@ -83,7 +83,6 @@ design -save gold
prep # calls wreduce
dump
select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
design -stash gate
@ -93,3 +92,27 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
##########
read_verilog <<EOT
module wreduce_sub_test4(input [3:0] i, output [8:0] o);
assign o = 5'b00010 - i;
endmodule
EOT
hierarchy -auto-top
proc
design -save gold
prep # calls wreduce
select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter