riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed handling of cell ports that aren't wires

This commit is contained in:
Andrew Zonenberg 2017-08-11 16:16:25 -07:00
parent 3dd7f42e2b
commit 2877d5e504
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
passes/opt/opt_rmports.cc
View File

@ -90,6 +90,9 @@ struct OptRmportsPass : public Pass {
for(int i=0; i<conn.second.size(); i++)
{
auto sig = conn.second[i].wire;
if(sig == NULL)
continue;
//log(" sig %s\n", sig->name.c_str());
if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) )
used_ports.emplace(sig->name);