mirror of https://github.com/YosysHQ/yosys.git
opt_rmports: Fixed incorrect handling of multi-bit nets
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66aac06eee
commit
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@ -56,14 +56,28 @@ struct OptRmportsPass : public Pass {
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auto& conns = module->connections();
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for(auto sigsig : conns)
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{
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auto s1 = sigsig.first.as_wire();
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auto s2 = sigsig.second.as_wire();
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auto s1 = sigsig.first;
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auto s2 = sigsig.second;
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if( (s1->port_input || s1->port_output) && (used_ports.find(s1->name) == used_ports.end()) )
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used_ports.emplace(s1->name);
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int len1 = s1.size();
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int len2 = s2.size();
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int len = len1;
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if(len2 < len1)
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len = len2;
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if( (s2->port_input || s2->port_output) && (used_ports.find(s2->name) == used_ports.end()) )
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used_ports.emplace(s2->name);
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for(int i=0; i<len; i++)
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{
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auto w1 = s1[i].wire;
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auto w2 = s2[i].wire;
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//log(" conn %s, %s\n", w1->name.c_str(), w2->name.c_str());
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if( (w1->port_input || w1->port_output) && (used_ports.find(w1->name) == used_ports.end()) )
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used_ports.emplace(w1->name);
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if( (w2->port_input || w2->port_output) && (used_ports.find(w2->name) == used_ports.end()) )
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used_ports.emplace(w2->name);
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}
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}
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//Then check connections to cells
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@ -73,12 +87,13 @@ struct OptRmportsPass : public Pass {
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auto& cconns = cell->connections();
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for(auto conn : cconns)
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{
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if(!conn.second.is_wire())
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continue;
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auto sig = conn.second.as_wire();
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if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) )
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used_ports.emplace(sig->name);
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for(int i=0; i<conn.second.size(); i++)
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{
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auto sig = conn.second[i].wire;
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//log(" sig %s\n", sig->name.c_str());
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if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) )
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used_ports.emplace(sig->name);
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}
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}
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}
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