mirror of https://github.com/YosysHQ/yosys.git
Added "abc -I <num> -P <num>"
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@ -32,13 +32,13 @@
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#define ABC_COMMAND_LIB "strash; scorr; ifraig; retime -o {D}; strash; dch -f; map {D}"
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#define ABC_COMMAND_CTR "strash; scorr; ifraig; retime -o {D}; strash; dch -f; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
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#define ABC_COMMAND_LUT "strash; scorr; ifraig; retime -o; strash; dch -f; if; mfs"
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#define ABC_COMMAND_SOP "strash; scorr; ifraig; retime -o; strash; dch -f; cover"
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#define ABC_COMMAND_SOP "strash; scorr; ifraig; retime -o; strash; dch -f; cover {I} {P}"
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#define ABC_COMMAND_DFL "strash; scorr; ifraig; retime -o; strash; dch -f; map"
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#define ABC_FAST_COMMAND_LIB "retime -o {D}; map {D}"
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#define ABC_FAST_COMMAND_CTR "retime -o {D}; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
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#define ABC_FAST_COMMAND_LUT "retime -o; if"
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#define ABC_FAST_COMMAND_SOP "retime -o; cover"
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#define ABC_FAST_COMMAND_SOP "retime -o; cover -I {I} -P {P}"
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#define ABC_FAST_COMMAND_DFL "retime -o; map"
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#include "kernel/register.h"
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@ -595,7 +595,8 @@ struct abc_output_filter
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void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
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std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
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bool keepff, std::string delay_target, bool fast_mode, const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode)
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bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, bool fast_mode,
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const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode)
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{
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module = current_module;
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map_autoidx = autoidx++;
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@ -662,6 +663,12 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
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abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
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for (size_t pos = abc_script.find("{I}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
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abc_script = abc_script.substr(0, pos) + sop_inputs + abc_script.substr(pos+3);
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for (size_t pos = abc_script.find("{P}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
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abc_script = abc_script.substr(0, pos) + sop_products + abc_script.substr(pos+3);
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abc_script += stringf("; write_blif %s/output.blif", tempdir_name.c_str());
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abc_script = add_echos_to_abc_cmd(abc_script);
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@ -1250,6 +1257,14 @@ struct AbcPass : public Pass {
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log(" set delay target. the string {D} in the default scripts above is\n");
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log(" replaced by this option when used, and an empty string otherwise.\n");
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log("\n");
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log(" -I <num>\n");
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log(" maximum number of SOP inputs.\n");
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log(" (replaces {I} in the default scripts above)\n");
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log("\n");
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log(" -P <num>\n");
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log(" maximum number of SOP products.\n");
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log(" (replaces {P} in the default scripts above)\n");
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log("\n");
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log(" -lut <width>\n");
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log(" generate netlist using luts of (max) the specified width.\n");
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log("\n");
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@ -1264,7 +1279,7 @@ struct AbcPass : public Pass {
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log(" 2, 3, .. inputs.\n");
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log("\n");
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log(" -sop\n");
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log(" map to sum-of-product cells\n");
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log(" map to sum-of-product cells and inverters\n");
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log("\n");
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// log(" -mux4, -mux8, -mux16\n");
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// log(" try to extract 4-input, 8-input, and/or 16-input muxes\n");
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@ -1320,7 +1335,8 @@ struct AbcPass : public Pass {
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#else
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std::string exe_file = proc_self_dirname() + "yosys-abc";
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#endif
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std::string script_file, liberty_file, constr_file, clk_str, delay_target;
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std::string script_file, liberty_file, constr_file, clk_str;
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std::string delay_target, sop_inputs, sop_products;
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bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
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bool show_tempdir = false, sop_mode = false;
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vector<int> lut_costs;
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@ -1372,6 +1388,14 @@ struct AbcPass : public Pass {
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delay_target = "-D " + args[++argidx];
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continue;
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}
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if (arg == "-I" && argidx+1 < args.size()) {
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sop_inputs = "-I " + args[++argidx];
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continue;
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}
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if (arg == "-P" && argidx+1 < args.size()) {
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sop_products = "-P " + args[++argidx];
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continue;
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}
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if (arg == "-lut" && argidx+1 < args.size()) {
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string arg = args[++argidx];
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size_t pos = arg.find_first_of(':');
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@ -1483,7 +1507,8 @@ struct AbcPass : public Pass {
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if (mod->processes.size() > 0)
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log("Skipping module %s as it contains processes.\n", log_id(mod));
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else if (!dff_mode || !clk_str.empty())
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abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff, delay_target, fast_mode, mod->selected_cells(), show_tempdir, sop_mode);
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abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
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delay_target, sop_inputs, sop_products, fast_mode, mod->selected_cells(), show_tempdir, sop_mode);
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else
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{
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assign_map.set(mod);
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@ -1627,8 +1652,8 @@ struct AbcPass : public Pass {
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clk_sig = assign_map(std::get<1>(it.first));
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en_polarity = std::get<2>(it.first);
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en_sig = assign_map(std::get<3>(it.first));
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abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs,
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!clk_sig.empty(), "$", keepff, delay_target, fast_mode, it.second, show_tempdir, sop_mode);
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abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
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keepff, delay_target, sop_inputs, sop_products, fast_mode, it.second, show_tempdir, sop_mode);
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assign_map.set(mod);
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}
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}
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