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Fix a bug in clk2fflogic memory handling

This commit is contained in:
Clifford Wolf 2017-12-14 02:29:19 +01:00
parent 590e6961cb
commit 6132e6e72a
1 changed files with 1 additions and 1 deletions
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2
passes/sat/clk2fflogic.cc
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@ -126,7 +126,7 @@ struct Clk2fflogicPass : public Pass {
SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);
SigSpec en_q = module->addWire(NEW_ID, GetSize(addr));
SigSpec en_q = module->addWire(NEW_ID, GetSize(en));
module->addFf(NEW_ID, en, en_q);
SigSpec addr_q = module->addWire(NEW_ID, GetSize(addr));