mirror of https://github.com/YosysHQ/yosys.git
added one more suggestion to optimize MUXes in pass "opt_const"
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@ -125,6 +125,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module)
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if (input.match(" 1")) ACTION_DO("\\Y", input.extract(1, 1));
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#ifdef MUX_UNDEF_SEL_TO_UNDEF_RESULTS
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if (input.match("01 ")) ACTION_DO("\\Y", input.extract(0, 1));
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// TODO: "10 " -> replace with "!S" gate
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// TODO: "0 " -> replace with "B AND S" gate
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// TODO: " 1 " -> replace with "A OR S" gate
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// TODO: "1 " -> replace with "B OR !S" gate
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