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Fixed "flatten" top-module detection: Only use on fully selected designs

This commit is contained in:
Clifford Wolf 2013-11-24 14:10:46 +01:00
parent 981677cf09
commit 72b35e0b99
1 changed files with 4 additions and 3 deletions
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7
passes/techmap/techmap.cc
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@ -501,9 +501,10 @@ struct FlattenPass : public Pass {
celltypeMap[it.first].insert(it.first);
RTLIL::Module *top_mod = NULL;
for (auto &mod_it : design->modules)
if (mod_it.second->get_bool_attribute("\\top"))
top_mod = mod_it.second;
if (design->full_selection())
for (auto &mod_it : design->modules)
if (mod_it.second->get_bool_attribute("\\top"))
top_mod = mod_it.second;
bool did_something = true;
std::set<RTLIL::Cell*> handled_cells;