mirror of https://github.com/YosysHQ/yosys.git
Added "setparam -type"
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042b67f024
commit
3655d7fea7
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@ -134,15 +134,18 @@ struct SetparamPass : public Pass {
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" setparam [ -set name value | -unset name ]... [selection]\n");
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log(" setparam [ -type cell_type ] [ -set name value | -unset name ]... [selection]\n");
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log("\n");
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log("Set/unset the given parameters on the selected cells. String values must be\n");
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log("passed in double quotes (\").\n");
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log("\n");
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log("The -type option can be used to change the cell type of the selected cells.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::vector<setunset_t> setunset_list;
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vector<setunset_t> setunset_list;
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string new_cell_type;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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@ -158,6 +161,10 @@ struct SetparamPass : public Pass {
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setunset_list.push_back(setunset_t(args[++argidx]));
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continue;
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}
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if (arg == "-type" && argidx+1 < args.size()) {
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new_cell_type = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -170,8 +177,11 @@ struct SetparamPass : public Pass {
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continue;
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for (auto &it : module->cells_)
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if (design->selected(module, it.second))
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if (design->selected(module, it.second)) {
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if (!new_cell_type.empty())
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it.second->type = new_cell_type;
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do_setunset(it.second->parameters, setunset_list);
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}
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}
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}
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} SetparamPass;
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